forked from eden-emu/eden
added missing skyeye mmu code
This commit is contained in:
bunnei
parent
56846a4200
commit
9a642caee7
12 changed files with 3333 additions and 44 deletions
307
src/core/arm/interpreter/mmu/tlb.cpp
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307
src/core/arm/interpreter/mmu/tlb.cpp
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#include <assert.h>
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#include "core/arm/interpreter/armdefs.h"
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ARMword tlb_masks[] = {
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0x00000000, /* TLB_INVALID */
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0xFFFFF000, /* TLB_SMALLPAGE */
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0xFFFF0000, /* TLB_LARGEPAGE */
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0xFFF00000, /* TLB_SECTION */
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0xFFFFF000, /*TLB_ESMALLPAGE, have TEX attirbute, only for XScale */
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0xFFFFFC00 /* TLB_TINYPAGE */
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};
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/* This function encodes table 8-2 Interpreting AP bits,
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returning non-zero if access is allowed. */
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static int
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check_perms (ARMul_State * state, int ap, int read)
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{
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int s, r, user;
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s = state->mmu.control & CONTROL_SYSTEM;
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r = state->mmu.control & CONTROL_ROM;
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//chy 2006-02-15 , should consider system mode, don't conside 26bit mode
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user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE);
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switch (ap) {
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case 0:
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return read && ((s && !user) || r);
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case 1:
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return !user;
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case 2:
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return read || !user;
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case 3:
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return 1;
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}
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return 0;
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}
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fault_t
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check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
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int read)
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{
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int access;
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state->mmu.last_domain = tlb->domain;
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access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3;
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if ((access == 0) || (access == 2)) {
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/* It's unclear from the documentation whether this
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should always raise a section domain fault, or if
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it should be a page domain fault in the case of an
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L1 that describes a page table. In the ARM710T
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datasheets, "Figure 8-9: Sequence for checking faults"
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seems to indicate the former, while "Table 8-4: Priority
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encoding of fault status" gives a value for FS[3210] in
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the event of a domain fault for a page. Hmm. */
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return SECTION_DOMAIN_FAULT;
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}
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if (access == 1) {
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/* client access - check perms */
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int subpage, ap;
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switch (tlb->mapping) {
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/*ks 2004-05-09
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* only for XScale
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* Extend Small Page(ESP) Format
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* 31-12 bits the base addr of ESP
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* 11-10 bits SBZ
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* 9-6 bits TEX
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* 5-4 bits AP
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* 3 bit C
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* 2 bit B
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* 1-0 bits 11
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* */
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case TLB_ESMALLPAGE: //xj
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subpage = 0;
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//printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr );
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break;
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case TLB_TINYPAGE:
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subpage = 0;
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//printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr );
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break;
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case TLB_SMALLPAGE:
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subpage = (virt_addr >> 10) & 3;
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break;
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case TLB_LARGEPAGE:
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subpage = (virt_addr >> 14) & 3;
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break;
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case TLB_SECTION:
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subpage = 3;
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break;
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default:
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assert (0);
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subpage = 0; /* cleans a warning */
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}
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ap = (tlb->perms >> (subpage * 2 + 4)) & 3;
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if (!check_perms (state, ap, read)) {
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if (tlb->mapping == TLB_SECTION) {
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return SECTION_PERMISSION_FAULT;
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}
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else {
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return SUBPAGE_PERMISSION_FAULT;
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}
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}
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}
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else { /* access == 3 */
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/* manager access - don't check perms */
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}
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return NO_FAULT;
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}
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fault_t
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translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
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tlb_entry_t ** tlb)
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{
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*tlb = mmu_tlb_search (state, tlb_t, virt_addr);
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if (!*tlb) {
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/* walk the translation tables */
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ARMword l1addr, l1desc;
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tlb_entry_t entry;
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l1addr = state->mmu.translation_table_base & 0xFFFFC000;
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l1addr = (l1addr | (virt_addr >> 18)) & ~3;
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//l1desc = mem_read_word (state, l1addr);
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bus_read(32, l1addr, &l1desc);
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switch (l1desc & 3) {
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case 0:
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/*
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* according to Figure 3-9 Sequence for checking faults in arm manual,
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* section translation fault should be returned here.
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*/
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{
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return SECTION_TRANSLATION_FAULT;
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}
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case 3:
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/* fine page table */
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// dcl 2006-01-08
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{
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ARMword l2addr, l2desc;
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l2addr = l1desc & 0xFFFFF000;
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l2addr = (l2addr |
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((virt_addr & 0x000FFC00) >> 8)) &
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~3;
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//l2desc = mem_read_word (state, l2addr);
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bus_read(32, l2addr, &l2desc);
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entry.virt_addr = virt_addr;
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entry.phys_addr = l2desc;
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entry.perms = l2desc & 0x00000FFC;
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entry.domain = (l1desc >> 5) & 0x0000000F;
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switch (l2desc & 3) {
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case 0:
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state->mmu.last_domain = entry.domain;
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return PAGE_TRANSLATION_FAULT;
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case 3:
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entry.mapping = TLB_TINYPAGE;
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break;
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case 1:
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// this is untested
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entry.mapping = TLB_LARGEPAGE;
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break;
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case 2:
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// this is untested
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entry.mapping = TLB_SMALLPAGE;
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break;
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}
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}
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break;
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case 1:
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/* coarse page table */
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{
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ARMword l2addr, l2desc;
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l2addr = l1desc & 0xFFFFFC00;
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l2addr = (l2addr |
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((virt_addr & 0x000FF000) >> 10)) &
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~3;
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//l2desc = mem_read_word (state, l2addr);
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bus_read(32, l2addr, &l2desc);
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entry.virt_addr = virt_addr;
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entry.phys_addr = l2desc;
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entry.perms = l2desc & 0x00000FFC;
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entry.domain = (l1desc >> 5) & 0x0000000F;
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//printf("SKYEYE:PAGE virt_addr = %x,l1desc=%x,phys_addr=%x\n",virt_addr,l1desc,entry.phys_addr);
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//chy 2003-09-02 for xscale
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switch (l2desc & 3) {
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case 0:
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state->mmu.last_domain = entry.domain;
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return PAGE_TRANSLATION_FAULT;
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case 3:
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if (!state->is_XScale) {
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state->mmu.last_domain =
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entry.domain;
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return PAGE_TRANSLATION_FAULT;
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};
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//ks 2004-05-09 xscale shold use Extend Small Page
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//entry.mapping = TLB_SMALLPAGE;
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entry.mapping = TLB_ESMALLPAGE; //xj
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break;
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case 1:
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entry.mapping = TLB_LARGEPAGE;
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break;
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case 2:
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entry.mapping = TLB_SMALLPAGE;
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break;
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}
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}
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break;
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case 2:
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/* section */
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//printf("SKYEYE:WARNING: not implement section mapping incompletely\n");
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//printf("SKYEYE:SECTION virt_addr = %x,l1desc=%x\n",virt_addr,l1desc);
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//return SECTION_DOMAIN_FAULT;
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//#if 0
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entry.virt_addr = virt_addr;
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entry.phys_addr = l1desc;
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entry.perms = l1desc & 0x00000C0C;
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entry.domain = (l1desc >> 5) & 0x0000000F;
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entry.mapping = TLB_SECTION;
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break;
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//#endif
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}
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entry.virt_addr &= tlb_masks[entry.mapping];
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entry.phys_addr &= tlb_masks[entry.mapping];
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/* place entry in the tlb */
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*tlb = &tlb_t->entrys[tlb_t->cycle];
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tlb_t->cycle = (tlb_t->cycle + 1) % tlb_t->num;
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**tlb = entry;
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}
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state->mmu.last_domain = (*tlb)->domain;
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return NO_FAULT;
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}
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int
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mmu_tlb_init (tlb_s * tlb_t, int num)
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{
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tlb_entry_t *e;
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int i;
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e = (tlb_entry_t *) malloc (sizeof (*e) * num);
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if (e == NULL) {
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ERROR_LOG(ARM11, "malloc size %d\n", sizeof (*e) * num);
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goto tlb_malloc_error;
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}
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tlb_t->entrys = e;
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for (i = 0; i < num; i++, e++)
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e->mapping = TLB_INVALID;
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tlb_t->cycle = 0;
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tlb_t->num = num;
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return 0;
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tlb_malloc_error:
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return -1;
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}
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void
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mmu_tlb_exit (tlb_s * tlb_t)
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{
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free (tlb_t->entrys);
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};
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void
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mmu_tlb_invalidate_all (ARMul_State * state, tlb_s * tlb_t)
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{
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int entry;
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for (entry = 0; entry < tlb_t->num; entry++) {
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tlb_t->entrys[entry].mapping = TLB_INVALID;
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}
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tlb_t->cycle = 0;
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}
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void
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mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr)
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{
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tlb_entry_t *tlb;
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tlb = mmu_tlb_search (state, tlb_t, addr);
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if (tlb) {
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tlb->mapping = TLB_INVALID;
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}
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}
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tlb_entry_t *
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mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t, ARMword virt_addr)
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{
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int entry;
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for (entry = 0; entry < tlb_t->num; entry++) {
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tlb_entry_t *tlb;
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ARMword mask;
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tlb = &(tlb_t->entrys[entry]);
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if (tlb->mapping == TLB_INVALID) {
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continue;
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}
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mask = tlb_masks[tlb->mapping];
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if ((virt_addr & mask) == (tlb->virt_addr & mask)) {
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return tlb;
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}
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}
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return NULL;
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}
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