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[dynarmic] attempt fix DBZ

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lizzie 2025-07-30 08:05:45 +01:00
parent aadf20047b
commit f3ac8fdfab
Signed by untrusted user: Lizzie
GPG key ID: D9E134A23AD395CE
2 changed files with 16 additions and 22 deletions
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10
externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp vendored
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@ -573,9 +573,17 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
if (!is_xmm) {
// TODO(lizzie): Using lower (xmm0 and such) registers results in issues/crashes - INVESTIGATE WHY
// Intel recommends to spill GPR onto XMM registers IF POSSIBLE
for (auto const i : any_xmm)
// TODO(lizzie): Issues on DBZ, theory: Scratch XMM not properly restored after a function call?
// Must sync with ABI registers (except XMM0, XMM1 and XMM2)
#ifdef _WIN32
for (size_t i = size_t(HostLoc::XMM5); i >= size_t(HostLoc::XMM3); --i)
if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
return loc;
#else
for (size_t i = size_t(HostLoc::XMM15); i >= size_t(HostLoc::XMM3); --i)
if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
return loc;
#endif
}
// Otherwise go to stack spilling
for (size_t i = size_t(HostLoc::FirstSpill); i < hostloc_info.size(); ++i)

28
externals/dynarmic/src/dynarmic/ir/opcodes.cpp vendored
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@ -41,29 +41,15 @@ struct Meta {
};
// Evil macro magic for Intel C++ compiler
#define PP_ARG_N( \
_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
_11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \
_21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \
_31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \
_41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \
_51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \
_61, _62, _63, N, ...) N
#define PP_RSEQ_N() \
63, 62, 61, 60, \
59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \
49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \
39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \
29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \
19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
#define PP_NARG_(...) PP_ARG_N(__VA_ARGS__)
#define PP_NARG(...) (sizeof(#__VA_ARGS__) - 1 ? PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) : 0)
// Helper macro to force expanding __VA_ARGS__ to satisfy MSVC compiler.
#define PP_EXPAND(x) x
#define PP_NARGS(...) PP_EXPAND(PP_ARG_N(__VA_ARGS__, 5, 4, 3, 2, 1, 0))
#define PP_ARG_N(_1, _2, _3, _4, _5, N, ...) N
alignas(64) static const Meta opcode_info[] = {
#define OPCODE(name, type, ...) Meta{{__VA_ARGS__}, type, PP_NARG(__VA_ARGS__)},
#define A32OPC(name, type, ...) Meta{{__VA_ARGS__}, type, PP_NARG(__VA_ARGS__)},
#define A64OPC(name, type, ...) Meta{{__VA_ARGS__}, type, PP_NARG(__VA_ARGS__)},
#define OPCODE(name, type, ...) Meta{{__VA_ARGS__}, type, PP_EXPAND(PP_NARGS(__VA_ARGS__))},
#define A32OPC(name, type, ...) Meta{{__VA_ARGS__}, type, PP_EXPAND(PP_NARGS(__VA_ARGS__))},
#define A64OPC(name, type, ...) Meta{{__VA_ARGS__}, type, PP_EXPAND(PP_NARGS(__VA_ARGS__))},
#include "./opcodes.inc"
#undef OPCODE
#undef A32OPC