forked from eden-emu/eden
video_core: NVDEC Implementation
This commit aims to implement the NVDEC (Nvidia Decoder) functionality, with video frame decoding being handled by the FFmpeg library. The process begins with Ioctl commands being sent to the NVDEC and VIC (Video Image Composer) emulated devices. These allocate the necessary GPU buffers for the frame data, along with providing information on the incoming video data. A Submit command then signals the GPU to process and decode the frame data. To decode the frame, the respective codec's header must be manually composed from the information provided by NVDEC, then sent with the raw frame data to the ffmpeg library. Currently, H264 and VP9 are supported, with VP9 having some minor artifacting issues related mainly to the reference frame composition in its uncompressed header. Async GPU is not properly implemented at the moment. Co-Authored-By: David <25727384+ogniK5377@users.noreply.github.com>
This commit is contained in:
ameerj
parent
2f6ba54483
commit
eb67a45ca8
53 changed files with 4033 additions and 310 deletions
180
src/video_core/command_classes/vic.cpp
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src/video_core/command_classes/vic.cpp
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// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <array>
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#include "common/assert.h"
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#include "video_core/command_classes/nvdec.h"
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#include "video_core/command_classes/vic.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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#include "video_core/texture_cache/surface_params.h"
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extern "C" {
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#include <libswscale/swscale.h>
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}
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namespace Tegra {
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Vic::Vic(GPU& gpu_, std::shared_ptr<Nvdec> nvdec_processor_)
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: gpu(gpu_), nvdec_processor(std::move(nvdec_processor_)) {}
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Vic::~Vic() = default;
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void Vic::VicStateWrite(u32 offset, u32 arguments) {
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u8* const state_offset = reinterpret_cast<u8*>(&vic_state) + offset * sizeof(u32);
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std::memcpy(state_offset, &arguments, sizeof(u32));
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}
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void Vic::ProcessMethod(Vic::Method method, const std::vector<u32>& arguments) {
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LOG_DEBUG(HW_GPU, "Vic method 0x{:X}", static_cast<u32>(method));
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VicStateWrite(static_cast<u32>(method), arguments[0]);
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const u64 arg = static_cast<u64>(arguments[0]) << 8;
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switch (method) {
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case Method::Execute:
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Execute();
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break;
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case Method::SetConfigStructOffset:
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config_struct_address = arg;
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break;
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case Method::SetOutputSurfaceLumaOffset:
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output_surface_luma_address = arg;
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break;
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case Method::SetOutputSurfaceChromaUOffset:
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output_surface_chroma_u_address = arg;
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break;
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case Method::SetOutputSurfaceChromaVOffset:
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output_surface_chroma_v_address = arg;
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break;
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default:
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break;
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}
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}
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void Vic::Execute() {
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if (output_surface_luma_address == 0) {
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LOG_ERROR(Service_NVDRV, "VIC Luma address not set. Recieved 0x{:X}",
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vic_state.output_surface.luma_offset);
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return;
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}
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const VicConfig config{gpu.MemoryManager().Read<u64>(config_struct_address + 0x20)};
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const VideoPixelFormat pixel_format =
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static_cast<VideoPixelFormat>(config.pixel_format.Value());
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switch (pixel_format) {
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case VideoPixelFormat::BGRA8:
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case VideoPixelFormat::RGBA8: {
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LOG_TRACE(Service_NVDRV, "Writing RGB Frame");
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const auto* frame = nvdec_processor->GetFrame();
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if (!frame || frame->width == 0 || frame->height == 0) {
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return;
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}
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if (scaler_ctx == nullptr || frame->width != scaler_width ||
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frame->height != scaler_height) {
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const AVPixelFormat target_format =
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(pixel_format == VideoPixelFormat::RGBA8) ? AV_PIX_FMT_RGBA : AV_PIX_FMT_BGRA;
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sws_freeContext(scaler_ctx);
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scaler_ctx = nullptr;
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// FFmpeg returns all frames in YUV420, convert it into expected format
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scaler_ctx =
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sws_getContext(frame->width, frame->height, AV_PIX_FMT_YUV420P, frame->width,
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frame->height, target_format, 0, nullptr, nullptr, nullptr);
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scaler_width = frame->width;
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scaler_height = frame->height;
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}
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// Get Converted frame
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const std::size_t linear_size = frame->width * frame->height * 4;
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using AVMallocPtr = std::unique_ptr<u8, decltype(&av_free)>;
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AVMallocPtr converted_frame_buffer{static_cast<u8*>(av_malloc(linear_size)), av_free};
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const int converted_stride{frame->width * 4};
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u8* const converted_frame_buf_addr{converted_frame_buffer.get()};
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sws_scale(scaler_ctx, frame->data, frame->linesize, 0, frame->height,
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&converted_frame_buf_addr, &converted_stride);
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const u32 blk_kind = static_cast<u32>(config.block_linear_kind);
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if (blk_kind != 0) {
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// swizzle pitch linear to block linear
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const u32 block_height = static_cast<u32>(config.block_linear_height_log2);
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const auto size = Tegra::Texture::CalculateSize(true, 4, frame->width, frame->height, 1,
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block_height, 0);
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std::vector<u8> swizzled_data(size);
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Tegra::Texture::CopySwizzledData(frame->width, frame->height, 1, 4, 4,
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swizzled_data.data(), converted_frame_buffer.get(),
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false, block_height, 0, 1);
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, swizzled_data.data(), size);
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gpu.Maxwell3D().OnMemoryWrite();
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} else {
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// send pitch linear frame
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, converted_frame_buf_addr,
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linear_size);
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gpu.Maxwell3D().OnMemoryWrite();
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}
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break;
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}
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case VideoPixelFormat::Yuv420: {
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LOG_TRACE(Service_NVDRV, "Writing YUV420 Frame");
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const auto* frame = nvdec_processor->GetFrame();
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if (!frame || frame->width == 0 || frame->height == 0) {
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return;
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}
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const std::size_t surface_width = config.surface_width_minus1 + 1;
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const std::size_t surface_height = config.surface_height_minus1 + 1;
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const std::size_t half_width = surface_width / 2;
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const std::size_t half_height = config.surface_height_minus1 / 2;
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const std::size_t aligned_width = (surface_width + 0xff) & ~0xff;
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const auto* luma_ptr = frame->data[0];
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const auto* chroma_b_ptr = frame->data[1];
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const auto* chroma_r_ptr = frame->data[2];
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const auto stride = frame->linesize[0];
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const auto half_stride = frame->linesize[1];
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std::vector<u8> luma_buffer(aligned_width * surface_height);
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std::vector<u8> chroma_buffer(aligned_width * half_height);
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// Populate luma buffer
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for (std::size_t y = 0; y < surface_height - 1; ++y) {
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std::size_t src = y * stride;
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std::size_t dst = y * aligned_width;
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std::size_t size = surface_width;
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for (std::size_t offset = 0; offset < size; ++offset) {
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luma_buffer[dst + offset] = luma_ptr[src + offset];
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}
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}
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(),
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luma_buffer.size());
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// Populate chroma buffer from both channels with interleaving.
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for (std::size_t y = 0; y < half_height; ++y) {
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std::size_t src = y * half_stride;
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std::size_t dst = y * aligned_width;
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for (std::size_t x = 0; x < half_width; ++x) {
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chroma_buffer[dst + x * 2] = chroma_b_ptr[src + x];
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chroma_buffer[dst + x * 2 + 1] = chroma_r_ptr[src + x];
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}
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}
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gpu.MemoryManager().WriteBlock(output_surface_chroma_u_address, chroma_buffer.data(),
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chroma_buffer.size());
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gpu.Maxwell3D().OnMemoryWrite();
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unknown video pixel format {}", config.pixel_format.Value());
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break;
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}
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}
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} // namespace Tegra
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