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eden/src/shader_recompiler/frontend/maxwell/maxwell.inc

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shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
INST(AL2P, "AL2P", "1110 1111 1010 0---")
INST(ALD, "ALD", "1110 1111 1101 1---")
INST(AST, "AST", "1110 1111 1111 0---")
INST(ATOM_cas, "ATOM (cas)", "1110 1110 1111 ----")
INST(ATOM, "ATOM", "1110 1101 ---- ----")
INST(ATOMS_cas, "ATOMS (cas)", "1110 1110 ---- ----")
INST(ATOMS, "ATOMS", "1110 1100 ---- ----")
INST(B2R, "B2R", "1111 0000 1011 1---")
INST(BAR, "BAR", "1111 0000 1010 1---")
INST(BFE_reg, "BFE (reg)", "0101 1100 0000 0---")
INST(BFE_cbuf, "BFE (cbuf)", "0100 1100 0000 0---")
INST(BFE_imm, "BFE (imm)", "0011 100- 0000 0---")
INST(BFI_reg, "BFI (reg)", "0101 1011 1111 0---")
INST(BFI_rc, "BFI (rc)", "0101 0011 1111 0---")
INST(BFI_cr, "BFI (cr)", "0100 1011 1111 0---")
INST(BFI_imm, "BFI (imm)", "0011 011- 1111 0---")
INST(BPT, "BPT", "1110 0011 1010 ----")
INST(BRA, "BRA", "1110 0010 0100 ----")
INST(BRK, "BRK", "1110 0011 0100 ----")
INST(BRX, "BRX", "1110 0010 0101 ----")
INST(CAL, "CAL", "1110 0010 0110 ----")
INST(CCTL, "CCTL", "1110 1111 011- ----")
INST(CCTLL, "CCTLL", "1110 1111 100- ----")
INST(CONT, "CONT", "1110 0011 0101 ----")
INST(CS2R, "CS2R", "0101 0000 1100 1---")
INST(CSET, "CSET", "0101 0000 1001 1---")
INST(CSETP, "CSETP", "0101 0000 1010 0---")
INST(DADD_reg, "DADD (reg)", "0101 1100 0111 0---")
INST(DADD_cbuf, "DADD (cbuf)", "0100 1100 0111 0---")
INST(DADD_imm, "DADD (imm)", "0011 100- 0111 0---")
INST(DEPBAR, "DEPBAR", "1111 0000 1111 0---")
INST(DFMA_reg, "DFMA (reg)", "0101 1011 0111 ----")
INST(DFMA_rc, "DFMA (rc)", "0101 0011 0111 ----")
shader: Implement DMUL and DFMA Also add a missing const on DADD
2021-03-21 02:09:14 -04:00
INST(DFMA_cr, "DFMA (cr)", "0100 1011 0111 ----")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(DFMA_imm, "DFMA (imm)", "0011 011- 0111 ----")
shader: Implement DMNMX, DSET, DSETP
2021-03-21 19:28:37 -04:00
INST(DMNMX_reg, "DMNMX (reg)", "0101 1100 0101 0---")
INST(DMNMX_cbuf, "DMNMX (cbuf)", "0100 1100 0101 0---")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(DMNMX_imm, "DMNMX (imm)", "0011 100- 0101 0---")
INST(DMUL_reg, "DMUL (reg)", "0101 1100 1000 0---")
INST(DMUL_cbuf, "DMUL (cbuf)", "0100 1100 1000 0---")
INST(DMUL_imm, "DMUL (imm)", "0011 100- 1000 0---")
INST(DSET_reg, "DSET (reg)", "0101 1001 0--- ----")
INST(DSET_cbuf, "DSET (cbuf)", "0100 1001 0--- ----")
INST(DSET_imm, "DSET (imm)", "0011 001- 0--- ----")
INST(DSETP_reg, "DSETP (reg)", "0101 1011 1000 ----")
INST(DSETP_cbuf, "DSETP (cbuf)", "0100 1011 1000 ----")
INST(DSETP_imm, "DSETP (imm)", "0011 011- 1000 ----")
INST(EXIT, "EXIT", "1110 0011 0000 ----")
INST(F2F_reg, "F2F (reg)", "0101 1100 1010 1---")
INST(F2F_cbuf, "F2F (cbuf)", "0100 1100 1010 1---")
INST(F2F_imm, "F2F (imm)", "0011 100- 1010 1---")
INST(F2I_reg, "F2I (reg)", "0101 1100 1011 0---")
INST(F2I_cbuf, "F2I (cbuf)", "0100 1100 1011 0---")
INST(F2I_imm, "F2I (imm)", "0011 100- 1011 0---")
INST(FADD_reg, "FADD (reg)", "0101 1100 0101 1---")
INST(FADD_cbuf, "FADD (cbuf)", "0100 1100 0101 1---")
INST(FADD_imm, "FADD (imm)", "0011 100- 0101 1---")
INST(FADD32I, "FADD32I", "0000 10-- ---- ----")
INST(FCHK_reg, "FCHK (reg)", "0101 1100 1000 1---")
INST(FCHK_cbuf, "FCHK (cbuf)", "0100 1100 1000 1---")
INST(FCHK_imm, "FCHK (imm)", "0011 100- 1000 1---")
INST(FCMP_reg, "FCMP (reg)", "0101 1011 1010 ----")
INST(FCMP_rc, "FCMP (rc)", "0101 0011 1010 ----")
INST(FCMP_cr, "FCMP (cr)", "0100 1011 1010 ----")
INST(FCMP_imm, "FCMP (imm)", "0011 011- 1010 ----")
INST(FFMA_reg, "FFMA (reg)", "0101 1001 1--- ----")
INST(FFMA_rc, "FFMA (rc)", "0101 0001 1--- ----")
INST(FFMA_cr, "FFMA (cr)", "0100 1001 1--- ----")
INST(FFMA_imm, "FFMA (imm)", "0011 001- 1--- ----")
INST(FFMA32I, "FFMA32I", "0000 11-- ---- ----")
INST(FLO_reg, "FLO (reg)", "0101 1100 0011 0---")
INST(FLO_cbuf, "FLO (cbuf)", "0100 1100 0011 0---")
INST(FLO_imm, "FLO (imm)", "0011 100- 0011 0---")
INST(FMNMX_reg, "FMNMX (reg)", "0101 1100 0110 0---")
INST(FMNMX_cbuf, "FMNMX (cbuf)", "0100 1100 0110 0---")
INST(FMNMX_imm, "FMNMX (imm)", "0011 100- 0110 0---")
INST(FMUL_reg, "FMUL (reg)", "0101 1100 0110 1---")
INST(FMUL_cbuf, "FMUL (cbuf)", "0100 1100 0110 1---")
INST(FMUL_imm, "FMUL (imm)", "0011 100- 0110 1---")
INST(FMUL32I, "FMUL32I", "0001 1110 ---- ----")
INST(FSET_reg, "FSET (reg)", "0101 1000 ---- ----")
INST(FSET_cbuf, "FSET (cbuf)", "0100 1000 ---- ----")
INST(FSET_imm, "FSET (imm)", "0011 000- ---- ----")
INST(FSETP_reg, "FSETP (reg)", "0101 1011 1011 ----")
INST(FSETP_cbuf, "FSETP (cbuf)", "0100 1011 1011 ----")
INST(FSETP_imm, "FSETP (imm)", "0011 011- 1011 ----")
INST(FSWZADD, "FSWZADD", "0101 0000 1111 1---")
INST(GETCRSPTR, "GETCRSPTR", "1110 0010 1100 ----")
INST(GETLMEMBASE, "GETLMEMBASE", "1110 0010 1101 ----")
INST(HADD2_reg, "HADD2 (reg)", "0101 1101 0001 0---")
INST(HADD2_cbuf, "HADD2 (cbuf)", "0111 101- 1--- ----")
INST(HADD2_imm, "HADD2 (imm)", "0111 101- 0--- ----")
INST(HADD2_32I, "HADD2_32I", "0010 110- ---- ----")
INST(HFMA2_reg, "HFMA2 (reg)", "0101 1101 0000 0---")
INST(HFMA2_rc, "HFMA2 (rc)", "0110 0--- 1--- ----")
INST(HFMA2_cr, "HFMA2 (cr)", "0111 0--- 1--- ----")
INST(HFMA2_imm, "HFMA2 (imm)", "0111 0--- 0--- ----")
INST(HFMA2_32I, "HFMA2_32I", "0010 100- ---- ----")
INST(HMUL2_reg, "HMUL2 (reg)", "0101 1101 0000 1---")
INST(HMUL2_cbuf, "HMUL2 (cbuf)", "0111 100- 1--- ----")
INST(HMUL2_imm, "HMUL2 (imm)", "0111 100- 0--- ----")
INST(HMUL2_32I, "HMUL2_32I", "0010 101- ---- ----")
INST(HSET2_reg, "HSET2 (reg)", "0101 1101 0001 1---")
shader: Implement HSET2
2021-03-21 03:48:40 +01:00
INST(HSET2_cbuf, "HSET2 (cbuf)", "0111 110- 1--- ----")
INST(HSET2_imm, "HSET2 (imm)", "0111 110- 0--- ----")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(HSETP2_reg, "HSETP2 (reg)", "0101 1101 0010 0---")
INST(HSETP2_cbuf, "HSETP2 (cbuf)", "0111 111- 1--- ----")
INST(HSETP2_imm, "HSETP2 (imm)", "0111 111- 0--- ----")
INST(I2F_reg, "I2F (reg)", "0101 1100 1011 1---")
INST(I2F_cbuf, "I2F (cbuf)", "0100 1100 1011 1---")
INST(I2F_imm, "I2F (imm)", "0011 100- 1011 1---")
INST(I2I_reg, "I2I (reg)", "0101 1100 1110 0---")
INST(I2I_cbuf, "I2I (cbuf)", "0100 1100 1110 0---")
INST(I2I_imm, "I2I (imm)", "0011 100- 1110 0---")
INST(IADD_reg, "IADD (reg)", "0101 1100 0001 0---")
INST(IADD_cbuf, "IADD (cbuf)", "0100 1100 0001 0---")
INST(IADD_imm, "IADD (imm)", "0011 100- 0001 0---")
INST(IADD3_reg, "IADD3 (reg)", "0101 1100 1100 ----")
INST(IADD3_cbuf, "IADD3 (cbuf)", "0100 1100 1100 ----")
INST(IADD3_imm, "IADD3 (imm)", "0011 100- 1100 ----")
INST(IADD32I, "IADD32I", "0001 110- ---- ----")
INST(ICMP_reg, "ICMP (reg)", "0101 1011 0100 ----")
INST(ICMP_rc, "ICMP (rc)", "0101 0011 0100 ----")
INST(ICMP_cr, "ICMP (cr)", "0100 1011 0100 ----")
INST(ICMP_imm, "ICMP (imm)", "0011 011- 0100 ----")
INST(IDE, "IDE", "1110 0011 1001 ----")
INST(IDP_reg, "IDP (reg)", "0101 0011 1111 1---")
INST(IDP_imm, "IDP (imm)", "0101 0011 1101 1---")
INST(IMAD_reg, "IMAD (reg)", "0101 1010 0--- ----")
INST(IMAD_rc, "IMAD (rc)", "0101 0010 0--- ----")
INST(IMAD_cr, "IMAD (cr)", "0100 1010 0--- ----")
INST(IMAD_imm, "IMAD (imm)", "0011 010- 0--- ----")
INST(IMAD32I, "IMAD32I", "1000 00-- ---- ----")
INST(IMADSP_reg, "IMADSP (reg)", "0101 1010 1--- ----")
INST(IMADSP_rc, "IMADSP (rc)", "0101 0010 1--- ----")
INST(IMADSP_cr, "IMADSP (cr)", "0100 1010 1--- ----")
INST(IMADSP_imm, "IMADSP (imm)", "0011 010- 1--- ----")
INST(IMNMX_reg, "IMNMX (reg)", "0101 1100 0010 0---")
INST(IMNMX_cbuf, "IMNMX (cbuf)", "0100 1100 0010 0---")
INST(IMNMX_imm, "IMNMX (imm)", "0011 100- 0010 0---")
INST(IMUL_reg, "IMUL (reg)", "0101 1100 0011 1---")
INST(IMUL_cbuf, "IMUL (cbuf)", "0100 1100 0011 1---")
INST(IMUL_imm, "IMUL (imm)", "0011 100- 0011 1---")
INST(IMUL32I, "IMUL32I", "0001 1111 ---- ----")
INST(IPA, "IPA", "1110 0000 ---- ----")
INST(ISBERD, "ISBERD", "1110 1111 1101 0---")
INST(ISCADD_reg, "ISCADD (reg)", "0101 1100 0001 1---")
INST(ISCADD_cbuf, "ISCADD (cbuf)", "0100 1100 0001 1---")
INST(ISCADD_imm, "ISCADD (imm)", "0011 100- 0001 1---")
INST(ISCADD32I, "ISCADD32I", "0001 01-- ---- ----")
INST(ISET_reg, "ISET (reg)", "0101 1011 0101 ----")
INST(ISET_cbuf, "ISET (cbuf)", "0100 1011 0101 ----")
INST(ISET_imm, "ISET (imm)", "0011 011- 0101 ----")
INST(ISETP_reg, "ISETP (reg)", "0101 1011 0110 ----")
INST(ISETP_cbuf, "ISETP (cbuf)", "0100 1011 0110 ----")
INST(ISETP_imm, "ISETP (imm)", "0011 011- 0110 ----")
INST(JCAL, "JCAL", "1110 0010 0010 ----")
INST(JMP, "JMP", "1110 0010 0001 ----")
INST(JMX, "JMX", "1110 0010 0000 ----")
INST(KIL, "KIL", "1110 0011 0011 ----")
INST(LD, "LD", "100- ---- ---- ----")
INST(LDC, "LDC", "1110 1111 1001 0---")
INST(LDG, "LDG", "1110 1110 1101 0---")
INST(LDL, "LDL", "1110 1111 0100 0---")
INST(LDS, "LDS", "1110 1111 0100 1---")
INST(LEA_hi_reg, "LEA (hi reg)", "0101 1011 1101 1---")
INST(LEA_hi_cbuf, "LEA (hi cbuf)", "0001 10-- ---- ----")
INST(LEA_lo_reg, "LEA (lo reg)", "0101 1011 1101 0---")
INST(LEA_lo_cbuf, "LEA (lo cbuf)", "0100 1011 1101 ----")
INST(LEA_lo_imm, "LEA (lo imm)", "0011 011- 1101 0---")
INST(LEPC, "LEPC", "0101 0000 1101 0---")
INST(LONGJMP, "LONGJMP", "1110 0011 0001 ----")
INST(LOP_reg, "LOP (reg)", "0101 1100 0100 0---")
INST(LOP_cbuf, "LOP (cbuf)", "0100 1100 0100 0---")
INST(LOP_imm, "LOP (imm)", "0011 100- 0100 0---")
INST(LOP3_reg, "LOP3 (reg)", "0101 1011 1110 0---")
shader: Implement LOP and LOP3
2021-03-03 00:41:05 -05:00
INST(LOP3_cbuf, "LOP3 (cbuf)", "0000 001- ---- ----")
INST(LOP3_imm, "LOP3 (imm)", "0011 11-- ---- ----")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(LOP32I, "LOP32I", "0000 01-- ---- ----")
INST(MEMBAR, "MEMBAR", "1110 1111 1001 1---")
INST(MOV_reg, "MOV (reg)", "0101 1100 1001 1---")
INST(MOV_cbuf, "MOV (cbuf)", "0100 1100 1001 1---")
INST(MOV_imm, "MOV (imm)", "0011 100- 1001 1---")
INST(MOV32I, "MOV32I", "0000 0001 0000 ----")
INST(MUFU, "MUFU", "0101 0000 1000 0---")
INST(NOP, "NOP", "0101 0000 1011 0---")
INST(OUT_reg, "OUT (reg)", "1111 1011 1110 0---")
INST(OUT_cbuf, "OUT (cbuf)", "1110 1011 1110 0---")
INST(OUT_imm, "OUT (imm)", "1111 011- 1110 0---")
INST(P2R_reg, "P2R (reg)", "0101 1100 1110 1---")
INST(P2R_cbuf, "P2R (cbuf)", "0100 1100 1110 1---")
INST(P2R_imm, "P2R (imm)", "0011 1000 1110 1---")
INST(PBK, "PBK", "1110 0010 1010 ----")
INST(PCNT, "PCNT", "1110 0010 1011 ----")
INST(PEXIT, "PEXIT", "1110 0010 0011 ----")
INST(PIXLD, "PIXLD", "1110 1111 1110 1---")
INST(PLONGJMP, "PLONGJMP", "1110 0010 1000 ----")
INST(POPC_reg, "POPC (reg)", "0101 1100 0000 1---")
INST(POPC_cbuf, "POPC (cbuf)", "0100 1100 0000 1---")
INST(POPC_imm, "POPC (imm)", "0011 100- 0000 1---")
INST(PRET, "PRET", "1110 0010 0111 ----")
INST(PRMT_reg, "PRMT (reg)", "0101 1011 1100 ----")
INST(PRMT_rc, "PRMT (rc)", "0101 0011 1100 ----")
INST(PRMT_cr, "PRMT (cr)", "0100 1011 1100 ----")
INST(PRMT_imm, "PRMT (imm)", "0011 011- 1100 ----")
INST(PSET, "PSET", "0101 0000 1000 1---")
INST(PSETP, "PSETP", "0101 0000 1001 0---")
INST(R2B, "R2B", "1111 0000 1100 0---")
INST(R2P_reg, "R2P (reg)", "0101 1100 1111 0---")
INST(R2P_cbuf, "R2P (cbuf)", "0100 1100 1111 0---")
INST(R2P_imm, "R2P (imm)", "0011 100- 1111 0---")
INST(RAM, "RAM", "1110 0011 1000 ----")
INST(RED, "RED", "1110 1011 1111 1---")
INST(RET, "RET", "1110 0011 0010 ----")
INST(RRO_reg, "RRO (reg)", "0101 1100 1001 0---")
INST(RRO_cbuf, "RRO (cbuf)", "0100 1100 1001 0---")
INST(RRO_imm, "RRO (imm)", "0011 100- 1001 0---")
INST(RTT, "RTT", "1110 0011 0110 ----")
INST(S2R, "S2R", "1111 0000 1100 1---")
INST(SAM, "SAM", "1110 0011 0111 ----")
INST(SEL_reg, "SEL (reg)", "0101 1100 1010 0---")
INST(SEL_cbuf, "SEL (cbuf)", "0100 1100 1010 0---")
INST(SEL_imm, "SEL (imm)", "0011 100- 1010 0---")
INST(SETCRSPTR, "SETCRSPTR", "1110 0010 1110 ----")
INST(SETLMEMBASE, "SETLMEMBASE", "1110 0010 1111 ----")
INST(SHF_l_reg, "SHF (l reg)", "0101 1011 1111 1---")
INST(SHF_l_imm, "SHF (l imm)", "0011 011- 1111 1---")
INST(SHF_r_reg, "SHF (r reg)", "0101 1100 1111 1---")
INST(SHF_r_imm, "SHF (r imm)", "0011 100- 1111 1---")
INST(SHFL, "SHFL", "1110 1111 0001 0---")
INST(SHL_reg, "SHL (reg)", "0101 1100 0100 1---")
INST(SHL_cbuf, "SHL (cbuf)", "0100 1100 0100 1---")
INST(SHL_imm, "SHL (imm)", "0011 100- 0100 1---")
INST(SHR_reg, "SHR (reg)", "0101 1100 0010 1---")
INST(SHR_cbuf, "SHR (cbuf)", "0100 1100 0010 1---")
INST(SHR_imm, "SHR (imm)", "0011 100- 0010 1---")
INST(SSY, "SSY", "1110 0010 1001 ----")
INST(ST, "ST", "101- ---- ---- ----")
INST(STG, "STG", "1110 1110 1101 1---")
INST(STL, "STL", "1110 1111 0101 0---")
INST(STP, "STP", "1110 1110 1010 0---")
INST(STS, "STS", "1110 1111 0101 1---")
INST(SUATOM_cas, "SUATOM", "1110 1010 ---- ----")
INST(SULD, "SULD", "1110 1011 000- ----")
INST(SURED, "SURED", "1110 1011 010- ----")
INST(SUST, "SUST", "1110 1011 001- ----")
INST(SYNC, "SYNC", "1111 0000 1111 1---")
shader: Initial support for textures and TEX
2021-03-08 18:31:53 -03:00
INST(TEX, "TEX", "1100 0--- ---- ----")
INST(TEX_b, "TEX (b)", "1101 1110 10-- ----")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(TEXS, "TEXS", "1101 -00- ---- ----")
INST(TLD, "TLD", "1101 1100 --11 1---")
INST(TLD_b, "TLD (b)", "1101 1101 --11 1---")
shader: Implement TLD4 and TLD4_B
2021-03-24 23:41:55 +01:00
INST(TLD4, "TLD4", "1100 10-- ---- ----")
INST(TLD4_b, "TLD4 (b)", "1101 1110 11-- ----")
shader: Initial recompiler work
2021-01-09 03:30:07 -03:00
INST(TLD4S, "TLD4S", "1101 1111 -0-- ----")
INST(TLDS, "TLDS", "1101 -01- ---- ----")
INST(TMML, "TMML", "1101 1111 0101 1---")
INST(TMML_b, "TMML (b)", "1101 1111 0110 0---")
INST(TXA, "TXA", "1101 1111 0100 0---")
INST(TXD, "TXD", "1101 1110 0011 10--")
INST(TXD_b, "TXD (b)", "1101 1110 0111 10--")
INST(TXQ, "TXQ", "1101 1111 0100 1---")
INST(TXQ_b, "TXQ (b)", "1101 1111 0101 0---")
INST(VABSDIFF, "VABSDIFF", "0101 0100 ---- ----")
INST(VABSDIFF4, "VABSDIFF4", "0101 0000 0--- ----")
INST(VADD, "VADD", "0010 00-- ---- ----")
INST(VMAD, "VMAD", "0101 1111 ---- ----")
INST(VMNMX, "VMNMX", "0011 101- ---- ----")
INST(VOTE, "VOTE", "0101 0000 1101 1---")
INST(VOTE_vtg, "VOTE (vtg)", "0101 0000 1110 0---")
INST(VSET, "VSET", "0100 000- ---- ----")
INST(VSETP, "VSETP", "0101 0000 1111 0---")
INST(VSHL, "VSHL", "0101 0111 ---- ----")
INST(VSHR, "VSHR", "0101 0110 ---- ----")
INST(XMAD_reg, "XMAD (reg)", "0101 1011 00-- ----")
INST(XMAD_rc, "XMAD (rc)", "0101 0001 0--- ----")
INST(XMAD_cr, "XMAD (cr)", "0100 111- ---- ----")
INST(XMAD_imm, "XMAD (imm)", "0011 011- 00-- ----")
// Removed due to its weird formatting making fast tables larger
// INST(CCTLT, "CCTLT", "1110 1011 1111 0--0")
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