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4 changed files with 37 additions and 3 deletions
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@ -211,7 +211,11 @@ std::shared_ptr<Dynarmic::A32::Jit> ArmDynarmic32::MakeJit(Common::PageTable* pa
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config.enable_cycle_counting = !m_uses_wall_clock;
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config.enable_cycle_counting = !m_uses_wall_clock;
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// Code cache size - max in ARM is 128MiB, max in x86_64 is 2GiB
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// Code cache size - max in ARM is 128MiB, max in x86_64 is 2GiB
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#ifdef ARCHITECTURE_arm64
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config.code_cache_size = std::uint32_t(128_MiB);
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config.code_cache_size = std::uint32_t(128_MiB);
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#else
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config.code_cache_size = std::uint32_t(512_MiB);
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#endif
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// Allow memory fault handling to work
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// Allow memory fault handling to work
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if (m_system.DebuggerEnabled()) {
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if (m_system.DebuggerEnabled()) {
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@ -270,7 +270,11 @@ std::shared_ptr<Dynarmic::A64::Jit> ArmDynarmic64::MakeJit(Common::PageTable* pa
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config.enable_cycle_counting = !m_uses_wall_clock;
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config.enable_cycle_counting = !m_uses_wall_clock;
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// Code cache size - max in ARM is 128MiB, max in x86_64 is 2GiB
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// Code cache size - max in ARM is 128MiB, max in x86_64 is 2GiB
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#ifdef ARCHITECTURE_arm64
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config.code_cache_size = std::uint32_t(128_MiB);
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config.code_cache_size = std::uint32_t(128_MiB);
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#else
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config.code_cache_size = std::uint32_t(512_MiB);
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#endif
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// Allow memory fault handling to work
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// Allow memory fault handling to work
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if (m_system.DebuggerEnabled()) {
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if (m_system.DebuggerEnabled()) {
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@ -53,6 +53,19 @@ u32 HardwareComposer::ComposeLocked(f32* out_speed_scale, Display& display,
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// Set default speed limit to 100%.
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// Set default speed limit to 100%.
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*out_speed_scale = 1.0f;
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*out_speed_scale = 1.0f;
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// If no layers are available, skip the logic.
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bool any_visible = false;
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for (auto& layer : display.stack.layers) {
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if (layer->visible) {
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any_visible = true;
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break;
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}
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}
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if (!any_visible) {
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*out_speed_scale = 1.0f;
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return 1;
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}
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// Determine the number of vsync periods to wait before composing again.
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// Determine the number of vsync periods to wait before composing again.
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std::optional<s32> swap_interval{};
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std::optional<s32> swap_interval{};
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bool has_acquired_buffer{};
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bool has_acquired_buffer{};
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@ -110,7 +123,7 @@ u32 HardwareComposer::ComposeLocked(f32* out_speed_scale, Display& display,
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}
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}
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// If any new buffers were acquired, we can present.
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// If any new buffers were acquired, we can present.
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if (has_acquired_buffer) {
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if (has_acquired_buffer && !composition_stack.empty()) {
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// Sort by Z-index.
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// Sort by Z-index.
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std::stable_sort(composition_stack.begin(), composition_stack.end(),
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std::stable_sort(composition_stack.begin(), composition_stack.end(),
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[&](auto& l, auto& r) { return l.z_index < r.z_index; });
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[&](auto& l, auto& r) { return l.z_index < r.z_index; });
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@ -119,6 +132,19 @@ u32 HardwareComposer::ComposeLocked(f32* out_speed_scale, Display& display,
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nvdisp.Composite(composition_stack);
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nvdisp.Composite(composition_stack);
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}
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}
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// Batch framebuffer releases, instead of one-into-one.
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std::vector<std::pair<Layer*, Framebuffer*>> to_release;
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for (auto& [layer_id, framebuffer] : m_framebuffers) {
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if (framebuffer.release_frame_number > m_frame_number || !framebuffer.is_acquired)
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continue;
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if (auto layer = display.stack.FindLayer(layer_id); layer)
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to_release.emplace_back(layer.get(), &framebuffer);
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}
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for (auto& [layer, framebuffer] : to_release) {
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layer->buffer_item_consumer->ReleaseBuffer(framebuffer->item, android::Fence::NoFence());
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framebuffer->is_acquired = false;
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}
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// Advance by at least one frame.
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// Advance by at least one frame.
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const u32 frame_advance = swap_interval.value_or(1);
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const u32 frame_advance = swap_interval.value_or(1);
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m_frame_number += frame_advance;
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m_frame_number += frame_advance;
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@ -470,8 +470,8 @@ void PresentManager::CopyToSwapchainImpl(Frame* frame) {
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const std::array wait_semaphores = {present_semaphore, *frame->render_ready};
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const std::array wait_semaphores = {present_semaphore, *frame->render_ready};
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static constexpr std::array<VkPipelineStageFlags, 2> wait_stage_masks{
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static constexpr std::array<VkPipelineStageFlags, 2> wait_stage_masks{
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VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
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VK_PIPELINE_STAGE_TRANSFER_BIT,
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VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
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VK_PIPELINE_STAGE_TRANSFER_BIT,
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};
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};
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const VkSubmitInfo submit_info{
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const VkSubmitInfo submit_info{
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