[dynarmic] unconditional branches always take

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/dynarmic/docs/Design.md

@@ -273,52 +273,73 @@ Exclusive OR (i.e.: XOR)
 
 ### Callback: {Read,Write}Memory{8,16,32,64}
 
-    <u8> ReadMemory8(<u32> vaddr)
-    <u8> ReadMemory16(<u32> vaddr)
-    <u8> ReadMemory32(<u32> vaddr)
-    <u8> ReadMemory64(<u32> vaddr)
-    <void> WriteMemory8(<u32> vaddr, <u8> value_to_store)
-    <void> WriteMemory16(<u32> vaddr, <u16> value_to_store)
-    <void> WriteMemory32(<u32> vaddr, <u32> value_to_store)
-    <void> WriteMemory64(<u32> vaddr, <u64> value_to_store)
+```c++
+<u8> ReadMemory8(<u32> vaddr)
+<u8> ReadMemory16(<u32> vaddr)
+<u8> ReadMemory32(<u32> vaddr)
+<u8> ReadMemory64(<u32> vaddr)
+<void> WriteMemory8(<u32> vaddr, <u8> value_to_store)
+<void> WriteMemory16(<u32> vaddr, <u16> value_to_store)
+<void> WriteMemory32(<u32> vaddr, <u32> value_to_store)
+<void> WriteMemory64(<u32> vaddr, <u64> value_to_store)
+```
 
 Memory access.
 
 ### Terminal: Interpret
 
-    SetTerm(IR::Term::Interpret{next})
+```c++
+SetTerm(IR::Term::Interpret{next})
+```
 
 This terminal instruction calls the interpreter, starting at `next`.
 The interpreter must interpret exactly one instruction.
 
 ### Terminal: ReturnToDispatch
 
-    SetTerm(IR::Term::ReturnToDispatch{})
+```c++
+SetTerm(IR::Term::ReturnToDispatch{})
+```
 
 This terminal instruction returns control to the dispatcher.
 The dispatcher will use the value in R15 to determine what comes next.
 
 ### Terminal: LinkBlock
 
-    SetTerm(IR::Term::LinkBlock{next})
+```c++
+SetTerm(IR::Term::LinkBlock{next})
+```
 
 This terminal instruction jumps to the basic block described by `next` if we have enough
 cycles remaining. If we do not have enough cycles remaining, we return to the
 dispatcher, which will return control to the host.
 
+### Terminal: LinkBlockFast
+
+```c++
+SetTerm(IR::Term::LinkBlockFast{next})
+```
+
+This terminal instruction jumps to the basic block described by `next` unconditionally.
+This promises guarantees that must be held at runtime - i.e that the program wont hang,
+
 ### Terminal: PopRSBHint
 
-    SetTerm(IR::Term::PopRSBHint{})
+```c++
+SetTerm(IR::Term::PopRSBHint{})
+```
 
 This terminal instruction checks the top of the Return Stack Buffer against R15.
 If RSB lookup fails, control is returned to the dispatcher.
 This is an optimization for faster function calls. A backend that doesn't support
 this optimization or doesn't have a RSB may choose to implement this exactly as
-ReturnToDispatch.
+`ReturnToDispatch`.
 
 ### Terminal: If
 
-    SetTerm(IR::Term::If{cond, term_then, term_else})
+```c++
+SetTerm(IR::Term::If{cond, term_then, term_else})
+```
 
 This terminal instruction conditionally executes one terminal or another depending
 on the run-time state of the ARM flags.

src/dynarmic/docs/RegisterAllocator.md

@@ -19,6 +19,9 @@ The member functions on `RegAlloc` are just a combination of the above concepts.
 The following registers are reserved for internal use and should NOT participate in register allocation:
 - `%xmm0`, `%xmm1`, `%xmm2`: Used as scratch in exclusive memory access.
 - `%rsp`: Stack pointer.
+- `%r15`: JIT pointer
+- `%r14`: Page table pointer.
+- `%r13`: Fastmem pointer.
 
 The layout convenes `%r15` as the JIT state pointer - while it may be tempting to turn it into a synthetic pointer, keeping an entire register (out of 12 available) is preferable over inlining a directly computed immediate.
 

src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp

@@ -364,8 +364,7 @@ void BlockOfCode::GenRunCode(std::function<void(BlockOfCode&)> rcp) {
 
     cmp(dword[ABI_JIT_PTR + jsi.offsetof_halt_reason], 0);
     jne(return_to_caller_mxcsr_already_exited, T_NEAR);
-    lock();
-    or_(dword[ABI_JIT_PTR + jsi.offsetof_halt_reason], static_cast<u32>(HaltReason::Step));
+    lock(); or_(dword[ABI_JIT_PTR + jsi.offsetof_halt_reason], static_cast<u32>(HaltReason::Step));
 
     SwitchMxcsrOnEntry();
     jmp(ABI_PARAM2);
@@ -415,7 +414,6 @@ void BlockOfCode::GenRunCode(std::function<void(BlockOfCode&)> rcp) {
     }
 
     xor_(eax, eax);
-    lock();
     xchg(dword[ABI_JIT_PTR + jsi.offsetof_halt_reason], eax);
 
     ABI_PopCalleeSaveRegistersAndAdjustStack(*this, sizeof(StackLayout));

src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp

@@ -9,6 +9,7 @@
 #include "dynarmic/backend/x64/reg_alloc.h"
 
 #include <algorithm>
+#include <limits>
 #include <numeric>
 #include <utility>
 
@@ -152,19 +153,19 @@ bool Argument::GetImmediateU1() const noexcept {
 
 u8 Argument::GetImmediateU8() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
     return u32(imm);
 }
 

src/dynarmic/src/dynarmic/frontend/A64/translate/impl/a64_branch.cpp

@@ -20,9 +20,12 @@ bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
 bool TranslatorVisitor::B_uncond(Imm<26> imm26) {
     const s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
     const u64 target = ir.PC() + offset;
-
-    //ir.SetTerm(IR::Term::LinkBlockFast{ir.current_location->SetPC(target)});
-    ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
+    // Pattern to halt execution (B .)
+    if (target == ir.PC()) {
+        ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
+        return false;
+    }
+    ir.SetTerm(IR::Term::LinkBlockFast{ir.current_location->SetPC(target)});
     return false;
 }