shader: Add subgroup masks

src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp

@@ -10,6 +10,7 @@ namespace Shader::Maxwell {
 namespace {
 enum class SpecialRegister : u64 {
     SR_LANEID = 0,
+    SR_CLOCK = 1,
     SR_VIRTCFG = 2,
     SR_VIRTID = 3,
     SR_PM0 = 4,
@@ -20,6 +21,9 @@ enum class SpecialRegister : u64 {
     SR_PM5 = 9,
     SR_PM6 = 10,
     SR_PM7 = 11,
+    SR12 = 12,
+    SR13 = 13,
+    SR14 = 14,
     SR_ORDERING_TICKET = 15,
     SR_PRIM_TYPE = 16,
     SR_INVOCATION_ID = 17,
@@ -41,44 +45,70 @@ enum class SpecialRegister : u64 {
     SR_TID_X = 33,
     SR_TID_Y = 34,
     SR_TID_Z = 35,
+    SR_CTA_PARAM = 36,
     SR_CTAID_X = 37,
     SR_CTAID_Y = 38,
     SR_CTAID_Z = 39,
-    SR_NTID = 49,
-    SR_CirQueueIncrMinusOne = 50,
-    SR_NLATC = 51,
-    SR_SWINLO = 57,
-    SR_SWINSZ = 58,
-    SR_SMEMSZ = 59,
-    SR_SMEMBANKS = 60,
-    SR_LWINLO = 61,
-    SR_LWINSZ = 62,
-    SR_LMEMLOSZ = 63,
-    SR_LMEMHIOFF = 64,
-    SR_EQMASK = 65,
-    SR_LTMASK = 66,
-    SR_LEMASK = 67,
-    SR_GTMASK = 68,
-    SR_GEMASK = 69,
-    SR_REGALLOC = 70,
-    SR_GLOBALERRORSTATUS = 73,
-    SR_WARPERRORSTATUS = 75,
-    SR_PM_HI0 = 81,
-    SR_PM_HI1 = 82,
-    SR_PM_HI2 = 83,
-    SR_PM_HI3 = 84,
-    SR_PM_HI4 = 85,
-    SR_PM_HI5 = 86,
-    SR_PM_HI6 = 87,
-    SR_PM_HI7 = 88,
-    SR_CLOCKLO = 89,
-    SR_CLOCKHI = 90,
-    SR_GLOBALTIMERLO = 91,
-    SR_GLOBALTIMERHI = 92,
-    SR_HWTASKID = 105,
-    SR_CIRCULARQUEUEENTRYINDEX = 106,
-    SR_CIRCULARQUEUEENTRYADDRESSLOW = 107,
-    SR_CIRCULARQUEUEENTRYADDRESSHIGH = 108,
+    SR_NTID = 40,
+    SR_CirQueueIncrMinusOne = 41,
+    SR_NLATC = 42,
+    SR43 = 43,
+    SR_SM_SPA_VERSION = 44,
+    SR_MULTIPASSSHADERINFO = 45,
+    SR_LWINHI = 46,
+    SR_SWINHI = 47,
+    SR_SWINLO = 48,
+    SR_SWINSZ = 49,
+    SR_SMEMSZ = 50,
+    SR_SMEMBANKS = 51,
+    SR_LWINLO = 52,
+    SR_LWINSZ = 53,
+    SR_LMEMLOSZ = 54,
+    SR_LMEMHIOFF = 55,
+    SR_EQMASK = 56,
+    SR_LTMASK = 57,
+    SR_LEMASK = 58,
+    SR_GTMASK = 59,
+    SR_GEMASK = 60,
+    SR_REGALLOC = 61,
+    SR_BARRIERALLOC = 62,
+    SR63 = 63,
+    SR_GLOBALERRORSTATUS = 64,
+    SR65 = 65,
+    SR_WARPERRORSTATUS = 66,
+    SR_WARPERRORSTATUSCLEAR = 67,
+    SR68 = 68,
+    SR69 = 69,
+    SR70 = 70,
+    SR71 = 71,
+    SR_PM_HI0 = 72,
+    SR_PM_HI1 = 73,
+    SR_PM_HI2 = 74,
+    SR_PM_HI3 = 75,
+    SR_PM_HI4 = 76,
+    SR_PM_HI5 = 77,
+    SR_PM_HI6 = 78,
+    SR_PM_HI7 = 79,
+    SR_CLOCKLO = 80,
+    SR_CLOCKHI = 81,
+    SR_GLOBALTIMERLO = 82,
+    SR_GLOBALTIMERHI = 83,
+    SR84 = 84,
+    SR85 = 85,
+    SR86 = 86,
+    SR87 = 87,
+    SR88 = 88,
+    SR89 = 89,
+    SR90 = 90,
+    SR91 = 91,
+    SR92 = 92,
+    SR93 = 93,
+    SR94 = 94,
+    SR95 = 95,
+    SR_HWTASKID = 96,
+    SR_CIRCULARQUEUEENTRYINDEX = 97,
+    SR_CIRCULARQUEUEENTRYADDRESSLOW = 98,
+    SR_CIRCULARQUEUEENTRYADDRESSHIGH = 99,
 };
 
 [[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) {
@@ -103,6 +133,16 @@ enum class SpecialRegister : u64 {
         return ir.Imm32(Common::BitCast<u32>(1.0f));
     case SpecialRegister::SR_LANEID:
         return ir.LaneId();
+    case SpecialRegister::SR_EQMASK:
+        return ir.SubgroupEqMask();
+    case SpecialRegister::SR_LTMASK:
+        return ir.SubgroupLtMask();
+    case SpecialRegister::SR_LEMASK:
+        return ir.SubgroupLeMask();
+    case SpecialRegister::SR_GTMASK:
+        return ir.SubgroupGtMask();
+    case SpecialRegister::SR_GEMASK:
+        return ir.SubgroupGeMask();
     default:
         throw NotImplementedException("S2R special register {}", special_register);
     }