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Update src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp
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SDK-Chan 2025-08-04 11:31:20 +02:00
parent 7323ffeb45
commit ccbd4f4bfd
1 changed files with 4 additions and 1 deletions
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src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp
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@ -41,6 +41,7 @@ void TranslatorVisitor::ISBERD(u64 insn) {
} const isberd{insn}; } const isberd{insn};
bool is_only_skew_op = true; bool is_only_skew_op = true;
bool no_other_op = true;
auto apply_shift = [&](IR::U32 result) -> IR::U32 { auto apply_shift = [&](IR::U32 result) -> IR::U32 {
switch (isberd.shift.Value()) { switch (isberd.shift.Value()) {
case Shift::U16: case Shift::U16:
@ -69,6 +70,7 @@ void TranslatorVisitor::ISBERD(u64 insn) {
} }
is_only_skew_op = false; is_only_skew_op = false;
no_other_op = false;
X(isberd.dest_reg, result); X(isberd.dest_reg, result);
} }
@ -104,13 +106,14 @@ void TranslatorVisitor::ISBERD(u64 insn) {
} }
is_only_skew_op = false; is_only_skew_op = false;
no_other_op = false;
X(isberd.dest_reg, result_u32); X(isberd.dest_reg, result_u32);
} }
if (isberd.skew != 0 && is_only_skew_op) { if (isberd.skew != 0 && is_only_skew_op) {
IR::U32 result = ir.IAdd(X(isberd.src_reg), ir.LaneId()); IR::U32 result = ir.IAdd(X(isberd.src_reg), ir.LaneId());
X(isberd.dest_reg, result); X(isberd.dest_reg, result);
} else { } else if (no_other_op) {
X(isberd.dest_reg, X(isberd.src_reg)); X(isberd.dest_reg, X(isberd.src_reg));
} }
} }