From 8207f25b956bed00f0b1a8bac191b0be7cb90ec5 Mon Sep 17 00:00:00 2001 From: lizzie Date: Sun, 28 Sep 2025 18:03:09 +0000 Subject: [PATCH] [dynarmic] get rid of mcl intrusive list Signed-off-by: lizzie --- .../src/dynarmic/backend/x64/emit_x64.cpp | 5 ----- .../src/dynarmic/backend/x64/emit_x64.h | 2 -- src/dynarmic/src/dynarmic/ir/basic_block.cpp | 2 +- src/dynarmic/src/dynarmic/ir/basic_block.h | 5 ++--- src/dynarmic/src/dynarmic/ir/ir_emitter.h | 15 +++---------- .../src/dynarmic/ir/microinstruction.h | 5 ++--- src/dynarmic/src/dynarmic/ir/opt_passes.cpp | 22 +++++++++---------- 7 files changed, 19 insertions(+), 37 deletions(-) diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp index 3bc93e6fd5..3c41664464 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp @@ -38,11 +38,6 @@ EmitContext::EmitContext(RegAlloc& reg_alloc, IR::Block& block) EmitContext::~EmitContext() = default; -void EmitContext::EraseInstruction(IR::Inst* inst) { - block.Instructions().erase(inst); - inst->ClearArgs(); -} - EmitX64::EmitX64(BlockOfCode& code) : code(code) { exception_handler.Register(code); diff --git a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.h b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.h index fbe749b2ab..5f0019b62e 100644 --- a/src/dynarmic/src/dynarmic/backend/x64/emit_x64.h +++ b/src/dynarmic/src/dynarmic/backend/x64/emit_x64.h @@ -54,8 +54,6 @@ struct EmitContext { EmitContext(RegAlloc& reg_alloc, IR::Block& block); virtual ~EmitContext(); - void EraseInstruction(IR::Inst* inst); - virtual FP::FPCR FPCR(bool fpcr_controlled = true) const = 0; virtual bool HasOptimization(OptimizationFlag flag) const = 0; diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.cpp b/src/dynarmic/src/dynarmic/ir/basic_block.cpp index b00ab3cb20..6100303faa 100644 --- a/src/dynarmic/src/dynarmic/ir/basic_block.cpp +++ b/src/dynarmic/src/dynarmic/ir/basic_block.cpp @@ -46,7 +46,7 @@ Block::iterator Block::PrependNewInst(iterator insertion_point, Opcode opcode, s inst->SetArg(index, arg); index++; }); - return instructions.insert_before(insertion_point, inst); + return instructions.insert(insertion_point, *inst);; } static std::string TerminalToString(const Terminal& terminal_variant) noexcept { diff --git a/src/dynarmic/src/dynarmic/ir/basic_block.h b/src/dynarmic/src/dynarmic/ir/basic_block.h index e88dc92fc4..6757bfafc6 100644 --- a/src/dynarmic/src/dynarmic/ir/basic_block.h +++ b/src/dynarmic/src/dynarmic/ir/basic_block.h @@ -12,10 +12,9 @@ #include #include #include +#include -#include #include "dynarmic/common/common_types.h" - #include "dynarmic/ir/location_descriptor.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/terminal.h" @@ -35,7 +34,7 @@ enum class Opcode; class Block final { public: //using instruction_list_type = dense_list; - using instruction_list_type = mcl::intrusive_list; + using instruction_list_type = boost::intrusive::list; using size_type = instruction_list_type::size_type; using iterator = instruction_list_type::iterator; using const_iterator = instruction_list_type::const_iterator; diff --git a/src/dynarmic/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/src/dynarmic/ir/ir_emitter.h index dba34bcc56..6f00cec8ac 100644 --- a/src/dynarmic/src/dynarmic/ir/ir_emitter.h +++ b/src/dynarmic/src/dynarmic/ir/ir_emitter.h @@ -10,10 +10,10 @@ #include -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/assert.h" #include +#include "dynarmic/common/common_types.h" +#include "dynarmic/common/assert.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/acc_type.h" #include "dynarmic/ir/basic_block.h" @@ -124,7 +124,7 @@ public: ASSERT(value.GetType() == Type::U64); return value; } - ASSERT_FALSE("Invalid bitsize"); + ASSERT_MSG(false, "Invalid bitsize"); } U32 LeastSignificantWord(const U64& value) { @@ -2950,19 +2950,10 @@ public: block.SetTerminal(terminal); } - void SetInsertionPointBefore(IR::Inst* new_insertion_point) { - insertion_point = IR::Block::iterator{*new_insertion_point}; - } - void SetInsertionPointBefore(IR::Block::iterator new_insertion_point) { insertion_point = new_insertion_point; } - void SetInsertionPointAfter(IR::Inst* new_insertion_point) { - insertion_point = IR::Block::iterator{*new_insertion_point}; - ++insertion_point; - } - void SetInsertionPointAfter(IR::Block::iterator new_insertion_point) { insertion_point = new_insertion_point; ++insertion_point; diff --git a/src/dynarmic/src/dynarmic/ir/microinstruction.h b/src/dynarmic/src/dynarmic/ir/microinstruction.h index 6651aab7c5..9e8febfcd5 100644 --- a/src/dynarmic/src/dynarmic/ir/microinstruction.h +++ b/src/dynarmic/src/dynarmic/ir/microinstruction.h @@ -9,10 +9,9 @@ #pragma once #include +#include -#include #include "dynarmic/common/common_types.h" - #include "dynarmic/ir/value.h" #include "dynarmic/ir/opcodes.h" @@ -26,7 +25,7 @@ constexpr size_t max_arg_count = 4; /// A representation of a microinstruction. A single ARM/Thumb instruction may be /// converted into zero or more microinstructions. //class Inst final { -class Inst final : public mcl::intrusive_list_node { +class Inst final : public boost::intrusive::list_base_hook<> { public: explicit Inst(Opcode op) : op(op) {} diff --git a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp index 844e29023c..56815065fb 100644 --- a/src/dynarmic/src/dynarmic/ir/opt_passes.cpp +++ b/src/dynarmic/src/dynarmic/ir/opt_passes.cpp @@ -85,12 +85,10 @@ static void ConstantMemoryReads(IR::Block& block, A32::UserCallbacks* cb) { } static void FlagsPass(IR::Block& block) { - using Iterator = std::reverse_iterator; - struct FlagInfo { bool set_not_required = false; bool has_value_request = false; - Iterator value_request = {}; + IR::Block::reverse_iterator value_request = {}; }; struct ValuelessFlagInfo { bool set_not_required = false; @@ -101,7 +99,7 @@ static void FlagsPass(IR::Block& block) { FlagInfo c_flag; FlagInfo ge; - auto do_set = [&](FlagInfo& info, IR::Value value, Iterator inst) { + auto do_set = [&](FlagInfo& info, IR::Value value, IR::Block::reverse_iterator const inst) { if (info.has_value_request) { info.value_request->ReplaceUsesWith(value); } @@ -113,14 +111,14 @@ static void FlagsPass(IR::Block& block) { info.set_not_required = true; }; - auto do_set_valueless = [&](ValuelessFlagInfo& info, Iterator inst) { + auto do_set_valueless = [&](ValuelessFlagInfo& info, IR::Block::reverse_iterator const inst) { if (info.set_not_required) { inst->Invalidate(); } info.set_not_required = true; }; - auto do_get = [](FlagInfo& info, Iterator inst) { + auto do_get = [](FlagInfo& info, IR::Block::reverse_iterator const inst) { if (info.has_value_request) { info.value_request->ReplaceUsesWith(IR::Value{&*inst}); } @@ -447,7 +445,8 @@ static void A64CallbackConfigPass(IR::Block& block, const A64::UserConfig& conf) return; } - for (auto& inst : block) { + for (auto it = block.begin(); it != block.end(); it++) { + auto& inst = *it; if (inst.GetOpcode() != IR::Opcode::A64DataCacheOperationRaised) { continue; } @@ -456,7 +455,7 @@ static void A64CallbackConfigPass(IR::Block& block, const A64::UserConfig& conf) if (op == A64::DataCacheOperation::ZeroByVA) { A64::IREmitter ir{block}; ir.current_location = A64::LocationDescriptor{IR::LocationDescriptor{inst.GetArg(0).GetU64()}}; - ir.SetInsertionPointBefore(&inst); + ir.SetInsertionPointBefore(it); size_t bytes = 4 << static_cast(conf.dczid_el0 & 0b1111); IR::U64 addr{inst.GetArg(2)}; @@ -1243,7 +1242,7 @@ static void IdentityRemovalPass(IR::Block& block) { } if (inst.GetOpcode() == IR::Opcode::Identity || inst.GetOpcode() == IR::Opcode::Void) { - iter = block.Instructions().erase(inst); + iter = block.Instructions().erase(iter); to_invalidate.push_back(&inst); } else { ++iter; @@ -1405,8 +1404,9 @@ static void PolyfillPass(IR::Block& block, const PolyfillOptions& polyfill) { IR::IREmitter ir{block}; - for (auto& inst : block) { - ir.SetInsertionPointBefore(&inst); + for (auto it = block.begin(); it != block.end(); it++) { + auto& inst = *it; + ir.SetInsertionPointBefore(it); switch (inst.GetOpcode()) { case IR::Opcode::SHA256MessageSchedule0: