From 6f31a10699e7ac7d17224cea98d431db961cfde1 Mon Sep 17 00:00:00 2001 From: Producdevity Date: Wed, 30 Jul 2025 15:21:30 +0200 Subject: [PATCH] fix: reset submodules to match master and remove ffmpeg submodule --- .gitmodules | 3 + externals/CMakeLists.txt | 20 +- externals/SDL | 1 + externals/dynarmic/CMakeLists.txt | 6 +- externals/dynarmic/externals/CMakeLists.txt | 11 +- .../dynarmic/src/dynarmic/CMakeLists.txt | 108 +- .../dynarmic/backend/arm64/a32_interface.cpp | 7 +- .../dynarmic/backend/arm64/a32_jitstate.cpp | 5 +- .../src/dynarmic/backend/arm64/a32_jitstate.h | 5 +- .../dynarmic/backend/arm64/a64_interface.cpp | 7 +- .../src/dynarmic/backend/arm64/a64_jitstate.h | 5 +- .../src/dynarmic/backend/arm64/abi.cpp | 5 +- .../dynarmic/src/dynarmic/backend/arm64/abi.h | 8 +- .../dynarmic/backend/arm64/address_space.h | 5 +- .../src/dynarmic/backend/arm64/devirtualize.h | 5 +- .../src/dynarmic/backend/arm64/emit_arm64.h | 5 +- .../backend/arm64/emit_arm64_memory.h | 5 +- .../backend/arm64/exclusive_monitor.cpp | 5 +- .../src/dynarmic/backend/arm64/fastmem.h | 5 +- .../src/dynarmic/backend/arm64/fpsr_manager.h | 5 +- .../src/dynarmic/backend/arm64/reg_alloc.cpp | 7 +- .../src/dynarmic/backend/arm64/reg_alloc.h | 7 +- .../src/dynarmic/backend/arm64/stack_layout.h | 5 +- .../backend/arm64/verbose_debugging_output.h | 5 +- .../backend/block_range_information.cpp | 5 +- .../src/dynarmic/backend/exception_handler.h | 5 +- .../backend/exception_handler_macos.cpp | 7 +- .../backend/exception_handler_posix.cpp | 17 +- .../backend/riscv64/a32_address_space.cpp | 5 +- .../backend/riscv64/a32_interface.cpp | 7 +- .../dynarmic/backend/riscv64/a32_jitstate.cpp | 5 +- .../dynarmic/backend/riscv64/a32_jitstate.h | 5 +- .../src/dynarmic/backend/riscv64/code_block.h | 13 +- .../dynarmic/backend/riscv64/emit_riscv64.h | 5 +- .../dynarmic/backend/riscv64/reg_alloc.cpp | 7 +- .../src/dynarmic/backend/riscv64/reg_alloc.h | 7 +- .../dynarmic/backend/riscv64/stack_layout.h | 5 +- .../src/dynarmic/backend/x64/a32_emit_x64.cpp | 54 +- .../dynarmic/backend/x64/a32_interface.cpp | 7 +- .../src/dynarmic/backend/x64/a32_jitstate.cpp | 7 +- .../src/dynarmic/backend/x64/a32_jitstate.h | 5 +- .../src/dynarmic/backend/x64/a64_emit_x64.cpp | 14 +- .../backend/x64/a64_emit_x64_memory.cpp | 16 +- .../dynarmic/backend/x64/a64_interface.cpp | 5 +- .../src/dynarmic/backend/x64/a64_jitstate.h | 5 +- .../dynarmic/src/dynarmic/backend/x64/abi.cpp | 2 +- .../dynarmic/src/dynarmic/backend/x64/abi.h | 5 +- .../dynarmic/backend/x64/block_of_code.cpp | 14 +- .../src/dynarmic/backend/x64/block_of_code.h | 5 +- .../src/dynarmic/backend/x64/callback.h | 5 +- .../dynarmic/backend/x64/constant_pool.cpp | 5 +- .../src/dynarmic/backend/x64/constant_pool.h | 5 +- .../src/dynarmic/backend/x64/constants.h | 5 +- .../src/dynarmic/backend/x64/devirtualize.h | 5 +- .../src/dynarmic/backend/x64/emit_x64.cpp | 16 +- .../src/dynarmic/backend/x64/emit_x64_aes.cpp | 5 +- .../backend/x64/emit_x64_data_processing.cpp | 8 +- .../backend/x64/emit_x64_floating_point.cpp | 87 +- .../dynarmic/backend/x64/emit_x64_memory.h | 7 +- .../backend/x64/emit_x64_saturation.cpp | 7 +- .../dynarmic/backend/x64/emit_x64_vector.cpp | 7 +- .../x64/emit_x64_vector_floating_point.cpp | 44 +- .../x64/emit_x64_vector_saturation.cpp | 8 +- .../backend/x64/exception_handler_windows.cpp | 9 +- .../backend/x64/exclusive_monitor.cpp | 5 +- .../src/dynarmic/backend/x64/host_feature.h | 5 +- .../src/dynarmic/backend/x64/hostloc.h | 7 +- .../src/dynarmic/backend/x64/nzcv_util.h | 5 +- .../dynarmic/src/dynarmic/backend/x64/oparg.h | 5 +- .../src/dynarmic/backend/x64/reg_alloc.cpp | 62 +- .../src/dynarmic/backend/x64/reg_alloc.h | 9 +- .../src/dynarmic/backend/x64/stack_layout.h | 5 +- .../backend/x64/verbose_debugging_output.h | 5 +- .../dynarmic/src/dynarmic/common/atomic.h | 5 +- .../src/dynarmic/common/crypto/aes.cpp | 5 +- .../dynarmic/src/dynarmic/common/crypto/aes.h | 5 +- .../src/dynarmic/common/crypto/crc32.cpp | 5 +- .../src/dynarmic/common/crypto/crc32.h | 5 +- .../src/dynarmic/common/crypto/sm4.cpp | 5 +- .../dynarmic/src/dynarmic/common/crypto/sm4.h | 5 +- .../dynarmic/src/dynarmic/common/fp/fpcr.h | 7 +- .../dynarmic/src/dynarmic/common/fp/fpsr.h | 5 +- .../dynarmic/src/dynarmic/common/fp/info.h | 5 +- .../src/dynarmic/common/fp/mantissa_util.h | 5 +- .../src/dynarmic/common/fp/op/FPConvert.cpp | 5 +- .../src/dynarmic/common/fp/op/FPMulAdd.cpp | 5 +- .../dynarmic/common/fp/op/FPRSqrtEstimate.cpp | 5 +- .../dynarmic/common/fp/op/FPRecipEstimate.cpp | 7 +- .../dynarmic/common/fp/op/FPRecipExponent.cpp | 5 +- .../src/dynarmic/common/fp/op/FPRoundInt.cpp | 7 +- .../src/dynarmic/common/fp/op/FPRoundInt.h | 5 +- .../src/dynarmic/common/fp/op/FPToFixed.cpp | 7 +- .../src/dynarmic/common/fp/op/FPToFixed.h | 5 +- .../dynarmic/common/fp/process_exception.cpp | 5 +- .../src/dynarmic/common/fp/process_nan.cpp | 5 +- .../src/dynarmic/common/fp/unpacked.h | 5 +- .../src/dynarmic/common/llvm_disassemble.cpp | 7 +- .../src/dynarmic/common/llvm_disassemble.h | 5 +- .../dynarmic/src/dynarmic/common/math_util.h | 5 +- .../dynarmic/src/dynarmic/common/safe_ops.h | 5 +- .../dynarmic/src/dynarmic/common/u128.cpp | 5 +- externals/dynarmic/src/dynarmic/common/u128.h | 5 +- .../src/dynarmic/common/x64_disassemble.cpp | 5 +- .../src/dynarmic/common/x64_disassemble.h | 5 +- .../src/dynarmic/frontend/A32/FPSCR.h | 5 +- .../src/dynarmic/frontend/A32/ITState.h | 5 +- .../dynarmic/src/dynarmic/frontend/A32/PSR.h | 5 +- .../dynarmic/frontend/A32/a32_ir_emitter.cpp | 5 +- .../dynarmic/frontend/A32/a32_ir_emitter.h | 17 +- .../frontend/A32/a32_location_descriptor.h | 5 +- .../src/dynarmic/frontend/A32/a32_types.h | 7 +- .../src/dynarmic/frontend/A32/decoder/arm.h | 16 +- .../src/dynarmic/frontend/A32/decoder/asimd.h | 5 +- .../dynarmic/frontend/A32/decoder/thumb16.h | 5 +- .../dynarmic/frontend/A32/decoder/thumb32.h | 5 +- .../src/dynarmic/frontend/A32/decoder/vfp.h | 5 +- .../frontend/A32/disassembler/disassembler.h | 5 +- .../frontend/A32/translate/a32_translate.cpp | 48 - .../frontend/A32/translate/a32_translate.h | 5 +- .../A32/translate/conditional_state.cpp | 7 +- .../A32/translate/conditional_state.h | 5 +- .../A32/translate/impl/a32_translate_impl.cpp | 9 +- .../A32/translate/impl/a32_translate_impl.h | 7 +- .../A32/translate/impl/asimd_misc.cpp | 5 +- .../impl/asimd_one_reg_modified_immediate.cpp | 5 +- .../A32/translate/impl/asimd_three_regs.cpp | 6 +- .../translate/impl/asimd_two_regs_misc.cpp | 30 +- .../translate/impl/asimd_two_regs_scalar.cpp | 5 +- .../translate/impl/asimd_two_regs_shift.cpp | 41 +- .../frontend/A32/translate/impl/extension.cpp | 6 +- .../frontend/A32/translate/impl/saturated.cpp | 9 +- ...data_processing_plain_binary_immediate.cpp | 13 +- .../impl/thumb32_data_processing_register.cpp | 5 +- .../A32/translate/impl/thumb32_load_byte.cpp | 8 +- .../translate/impl/thumb32_load_halfword.cpp | 9 +- .../impl/thumb32_load_store_dual.cpp | 4 +- .../impl/thumb32_load_store_multiple.cpp | 4 +- .../A32/translate/impl/thumb32_load_word.cpp | 4 +- .../A32/translate/impl/thumb32_parallel.cpp | 8 +- .../frontend/A32/translate/translate_arm.cpp | 5 +- .../A32/translate/translate_thumb.cpp | 5 +- .../dynarmic/frontend/A64/a64_ir_emitter.cpp | 254 ++ .../dynarmic/frontend/A64/a64_ir_emitter.h | 318 +- .../frontend/A64/a64_location_descriptor.h | 5 +- .../src/dynarmic/frontend/A64/a64_types.h | 7 +- .../src/dynarmic/frontend/A64/decoder/a64.h | 21 +- .../frontend/A64/translate/a64_translate.cpp | 61 - .../frontend/A64/translate/a64_translate.h | 5 +- .../translate/impl/simd_scalar_pairwise.cpp | 20 +- .../impl/simd_scalar_shift_by_immediate.cpp | 58 +- .../translate/impl/simd_scalar_three_same.cpp | 10 +- .../impl/simd_scalar_two_register_misc.cpp | 52 +- .../impl/simd_scalar_x_indexed_element.cpp | 8 +- .../impl/simd_shift_by_immediate.cpp | 98 +- .../translate/impl/simd_three_different.cpp | 54 +- .../A64/translate/impl/simd_three_same.cpp | 140 +- .../translate/impl/simd_two_register_misc.cpp | 92 +- .../impl/simd_vector_x_indexed_element.cpp | 85 +- .../frontend/decoder/decoder_detail.h | 5 +- .../src/dynarmic/frontend/decoder/matcher.h | 5 +- .../dynarmic/src/dynarmic/frontend/imm.cpp | 7 +- .../dynarmic/src/dynarmic/frontend/imm.h | 7 +- .../src/dynarmic/interface/A32/arch_version.h | 4 +- .../src/dynarmic/interface/A32/config.h | 88 +- .../src/dynarmic/interface/A64/config.h | 137 +- .../dynarmic/src/dynarmic/ir/basic_block.cpp | 5 +- .../dynarmic/src/dynarmic/ir/basic_block.h | 5 +- .../dynarmic/src/dynarmic/ir/ir_emitter.cpp | 2877 ++++++++++++++- .../dynarmic/src/dynarmic/ir/ir_emitter.h | 3213 ++--------------- .../src/dynarmic/ir/location_descriptor.h | 5 +- .../src/dynarmic/ir/microinstruction.cpp | 5 +- .../src/dynarmic/ir/microinstruction.h | 5 +- externals/dynarmic/src/dynarmic/ir/opcodes.h | 5 +- .../ir/opt/a32_get_set_elimination_pass.cpp | 7 +- .../ir/opt/a64_get_set_elimination_pass.cpp | 5 +- .../ir/opt/a64_merge_interpret_blocks.cpp | 5 +- .../ir/opt/constant_propagation_pass.cpp | 7 +- .../src/dynarmic/ir/opt/verification_pass.cpp | 7 +- externals/dynarmic/src/dynarmic/ir/terminal.h | 5 +- externals/dynarmic/src/dynarmic/ir/type.h | 5 +- externals/dynarmic/src/dynarmic/ir/value.cpp | 5 +- externals/dynarmic/src/dynarmic/ir/value.h | 7 +- externals/dynarmic/tests/A32/fuzz_arm.cpp | 5 +- externals/dynarmic/tests/A32/fuzz_thumb.cpp | 5 +- .../tests/A32/test_arm_instructions.cpp | 3 +- .../tests/A32/test_thumb_instructions.cpp | 5 +- externals/dynarmic/tests/A32/testenv.h | 7 +- externals/dynarmic/tests/A64/a64.cpp | 250 +- externals/dynarmic/tests/A64/fibonacci.cpp | 5 +- externals/dynarmic/tests/A64/fp_min_max.cpp | 9 +- .../dynarmic/tests/A64/fuzz_with_unicorn.cpp | 8 +- .../tests/A64/misaligned_page_table.cpp | 3 +- .../dynarmic/tests/A64/test_invalidation.cpp | 8 +- externals/dynarmic/tests/A64/testenv.h | 7 +- externals/dynarmic/tests/decoder_tests.cpp | 5 +- externals/dynarmic/tests/fp/FPToFixed.cpp | 5 +- .../dynarmic/tests/fp/mantissa_util_tests.cpp | 5 +- .../dynarmic/tests/fp/unpacked_tests.cpp | 5 +- externals/dynarmic/tests/fuzz_util.cpp | 5 +- externals/dynarmic/tests/fuzz_util.h | 5 +- externals/dynarmic/tests/print_info.cpp | 5 +- externals/dynarmic/tests/rsqrt_test.cpp | 5 +- externals/dynarmic/tests/test_generator.cpp | 241 +- externals/dynarmic/tests/test_reader.cpp | 8 +- .../tests/unicorn_emu/a32_unicorn.cpp | 5 +- .../dynarmic/tests/unicorn_emu/a32_unicorn.h | 5 +- .../tests/unicorn_emu/a64_unicorn.cpp | 5 +- .../dynarmic/tests/unicorn_emu/a64_unicorn.h | 5 +- externals/ffmpeg/CMakeLists.txt | 13 +- .../tzdb_to_nx/externals/tz/CMakeLists.txt | 4 +- .../nx_tzdb/tzdb_to_nx/src/tzdb2nx/main.cpp | 9 +- .../nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.cpp | 37 +- .../nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.h | 39 +- externals/renderdoc/renderdoc_app.h | 29 +- externals/sirit/CMakeLists.txt | 2 +- 215 files changed, 4744 insertions(+), 5048 deletions(-) create mode 160000 externals/SDL diff --git a/.gitmodules b/.gitmodules index 10f9f7de96..8b00bfeeb0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -49,6 +49,9 @@ [submodule "externals/dynarmic/externals/zydis"] path = externals/dynarmic/externals/zydis url = https://github.com/zyantific/zydis.git +[submodule "externals/dynarmic/externals/xbyak"] + path = externals/dynarmic/externals/xbyak + url = https://github.com/herumi/xbyak.git [submodule "externals/nx_tzdb/tzdb_to_nx/externals/tz/tz"] path = externals/nx_tzdb/tzdb_to_nx/externals/tz/tz url = https://github.com/eggert/tz.git diff --git a/externals/CMakeLists.txt b/externals/CMakeLists.txt index cd7b80a33c..7dacba23b6 100644 --- a/externals/CMakeLists.txt +++ b/externals/CMakeLists.txt @@ -83,23 +83,7 @@ if (YUZU_USE_EXTERNAL_SDL2) set(SDL_FILE ON) endif() - include(CPM) - set(CPM_USE_LOCAL_PACKAGES OFF) - - if ("${YUZU_SYSTEM_PROFILE}" STREQUAL "steamdeck") - set(SDL_HASH cc016b0046) - set(SDL_PIPEWIRE OFF) # build errors out with this on - set(SDL_SHA512SUM 34d5ef58da6a4f9efa6689c82f67badcbd741f5a4f562a9c2c30828fa839830fb07681c5dc6a7851520e261c8405a416ac0a2c2513b51984fb3b4fa4dcb3e20b) - else() - set(SDL_HASH 2e4c12cd2c) - set(SDL_SHA512SUM d95af47f469a312876f8ab361074a1e7b8083db19935a102d9c6e5887ace6008e64475a8c54b00164b40cad86492bb1b2366084efdd0b2555e5fea6d9c5da80e) - endif() - - CPMAddPackage( - NAME SDL2 - URL "https://github.com/libsdl-org/SDL/archive/${SDL_HASH}.zip" - URL_HASH SHA512=${SDL_SHA512SUM} - ) + add_subdirectory(SDL) endif() # ENet @@ -227,7 +211,7 @@ if (ANDROID) endif() endif() -if ((CMAKE_SYSTEM_NAME STREQUAL "Linux" OR ANDROID) AND NOT TARGET gamemode::headers) +if (UNIX AND NOT APPLE AND NOT TARGET gamemode::headers) add_library(gamemode INTERFACE) target_include_directories(gamemode INTERFACE gamemode) add_library(gamemode::headers ALIAS gamemode) diff --git a/externals/SDL b/externals/SDL new file mode 160000 index 0000000000..2e4c12cd2c --- /dev/null +++ b/externals/SDL @@ -0,0 +1 @@ +Subproject commit 2e4c12cd2cb2c5d0b60ef2196b400339591e733c diff --git a/externals/dynarmic/CMakeLists.txt b/externals/dynarmic/CMakeLists.txt index 3db8d8077b..efb5edf165 100644 --- a/externals/dynarmic/CMakeLists.txt +++ b/externals/dynarmic/CMakeLists.txt @@ -98,7 +98,8 @@ else() -Wextra -Wcast-qual -pedantic - -Wno-missing-braces) + -Wno-missing-braces + -Wstack-usage=4096) if (ARCHITECTURE STREQUAL "x86_64") list(APPEND DYNARMIC_CXX_FLAGS -mtune=core2) @@ -122,15 +123,12 @@ else() # GCC knows that the variable is actually a Reg64. isMEM() will never return true for a # Reg64, but GCC doesn't know that. list(APPEND DYNARMIC_CXX_FLAGS -Wno-array-bounds) - list(APPEND DYNARMIC_CXX_FLAGS -Wstack-usage=4096) endif() if (CMAKE_CXX_COMPILER_ID MATCHES "[Cc]lang") # Bracket depth determines maximum size of a fold expression in Clang since 9c9974c3ccb6. # And this in turns limits the size of a std::array. list(APPEND DYNARMIC_CXX_FLAGS -fbracket-depth=1024) - # Clang mistakenly blames CMake for using unused arguments during compilation - list(APPEND DYNARMIC_CXX_FLAGS -Wno-unused-command-line-argument) endif() endif() diff --git a/externals/dynarmic/externals/CMakeLists.txt b/externals/dynarmic/externals/CMakeLists.txt index 67fb0f4190..f96497db7a 100644 --- a/externals/dynarmic/externals/CMakeLists.txt +++ b/externals/dynarmic/externals/CMakeLists.txt @@ -64,13 +64,12 @@ if (NOT TARGET ankerl::unordered_dense) endif() # xbyak -# uncomment if in an independent repo. -# if (NOT TARGET xbyak::xbyak) -# if ("x86_64" IN_LIST ARCHITECTURE) -# add_subdirectory(xbyak) -# endif() -# endif() +if (NOT TARGET xbyak::xbyak) + if ("x86_64" IN_LIST ARCHITECTURE) + add_subdirectory(xbyak) + endif() +endif() # zydis diff --git a/externals/dynarmic/src/dynarmic/CMakeLists.txt b/externals/dynarmic/src/dynarmic/CMakeLists.txt index ab2d653152..9227951fcc 100644 --- a/externals/dynarmic/src/dynarmic/CMakeLists.txt +++ b/externals/dynarmic/src/dynarmic/CMakeLists.txt @@ -5,10 +5,7 @@ add_library(dynarmic backend/block_range_information.h backend/exception_handler.h common/always_false.h - common/assert.cpp - common/assert.h common/cast_util.h - common/common_types.h common/crypto/aes.cpp common/crypto/aes.h common/crypto/crc32.cpp @@ -128,6 +125,52 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS) frontend/A32/translate/a32_translate.h frontend/A32/translate/conditional_state.cpp frontend/A32/translate/conditional_state.h + frontend/A32/translate/impl/a32_branch.cpp + frontend/A32/translate/impl/a32_crc32.cpp + frontend/A32/translate/impl/a32_exception_generating.cpp + frontend/A32/translate/impl/a32_translate_impl.cpp + frontend/A32/translate/impl/a32_translate_impl.h + frontend/A32/translate/impl/asimd_load_store_structures.cpp + frontend/A32/translate/impl/asimd_misc.cpp + frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp + frontend/A32/translate/impl/asimd_three_regs.cpp + frontend/A32/translate/impl/asimd_two_regs_misc.cpp + frontend/A32/translate/impl/asimd_two_regs_scalar.cpp + frontend/A32/translate/impl/asimd_two_regs_shift.cpp + frontend/A32/translate/impl/barrier.cpp + frontend/A32/translate/impl/coprocessor.cpp + frontend/A32/translate/impl/data_processing.cpp + frontend/A32/translate/impl/divide.cpp + frontend/A32/translate/impl/extension.cpp + frontend/A32/translate/impl/hint.cpp + frontend/A32/translate/impl/load_store.cpp + frontend/A32/translate/impl/misc.cpp + frontend/A32/translate/impl/multiply.cpp + frontend/A32/translate/impl/packing.cpp + frontend/A32/translate/impl/parallel.cpp + frontend/A32/translate/impl/reversal.cpp + frontend/A32/translate/impl/saturated.cpp + frontend/A32/translate/impl/status_register_access.cpp + frontend/A32/translate/impl/synchronization.cpp + frontend/A32/translate/impl/thumb16.cpp + frontend/A32/translate/impl/thumb32_branch.cpp + frontend/A32/translate/impl/thumb32_control.cpp + frontend/A32/translate/impl/thumb32_coprocessor.cpp + frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp + frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp + frontend/A32/translate/impl/thumb32_data_processing_register.cpp + frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp + frontend/A32/translate/impl/thumb32_load_byte.cpp + frontend/A32/translate/impl/thumb32_load_halfword.cpp + frontend/A32/translate/impl/thumb32_load_store_dual.cpp + frontend/A32/translate/impl/thumb32_load_store_multiple.cpp + frontend/A32/translate/impl/thumb32_load_word.cpp + frontend/A32/translate/impl/thumb32_long_multiply.cpp + frontend/A32/translate/impl/thumb32_misc.cpp + frontend/A32/translate/impl/thumb32_multiply.cpp + frontend/A32/translate/impl/thumb32_parallel.cpp + frontend/A32/translate/impl/thumb32_store_single_data_item.cpp + frontend/A32/translate/impl/vfp.cpp frontend/A32/translate/translate_arm.cpp frontend/A32/translate/translate_thumb.cpp interface/A32/a32.h @@ -151,6 +194,65 @@ if ("A64" IN_LIST DYNARMIC_FRONTENDS) frontend/A64/decoder/a64.inc frontend/A64/translate/a64_translate.cpp frontend/A64/translate/a64_translate.h + frontend/A64/translate/impl/a64_branch.cpp + frontend/A64/translate/impl/a64_exception_generating.cpp + frontend/A64/translate/impl/data_processing_addsub.cpp + frontend/A64/translate/impl/data_processing_bitfield.cpp + frontend/A64/translate/impl/data_processing_conditional_compare.cpp + frontend/A64/translate/impl/data_processing_conditional_select.cpp + frontend/A64/translate/impl/data_processing_crc32.cpp + frontend/A64/translate/impl/data_processing_logical.cpp + frontend/A64/translate/impl/data_processing_multiply.cpp + frontend/A64/translate/impl/data_processing_pcrel.cpp + frontend/A64/translate/impl/data_processing_register.cpp + frontend/A64/translate/impl/data_processing_shift.cpp + frontend/A64/translate/impl/floating_point_compare.cpp + frontend/A64/translate/impl/floating_point_conditional_compare.cpp + frontend/A64/translate/impl/floating_point_conditional_select.cpp + frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp + frontend/A64/translate/impl/floating_point_conversion_integer.cpp + frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp + frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp + frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp + frontend/A64/translate/impl/impl.cpp + frontend/A64/translate/impl/impl.h + frontend/A64/translate/impl/load_store_exclusive.cpp + frontend/A64/translate/impl/load_store_load_literal.cpp + frontend/A64/translate/impl/load_store_multiple_structures.cpp + frontend/A64/translate/impl/load_store_no_allocate_pair.cpp + frontend/A64/translate/impl/load_store_register_immediate.cpp + frontend/A64/translate/impl/load_store_register_pair.cpp + frontend/A64/translate/impl/load_store_register_register_offset.cpp + frontend/A64/translate/impl/load_store_register_unprivileged.cpp + frontend/A64/translate/impl/load_store_single_structure.cpp + frontend/A64/translate/impl/move_wide.cpp + frontend/A64/translate/impl/simd_across_lanes.cpp + frontend/A64/translate/impl/simd_aes.cpp + frontend/A64/translate/impl/simd_copy.cpp + frontend/A64/translate/impl/simd_crypto_four_register.cpp + frontend/A64/translate/impl/simd_crypto_three_register.cpp + frontend/A64/translate/impl/simd_extract.cpp + frontend/A64/translate/impl/simd_modified_immediate.cpp + frontend/A64/translate/impl/simd_permute.cpp + frontend/A64/translate/impl/simd_scalar_pairwise.cpp + frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp + frontend/A64/translate/impl/simd_scalar_three_same.cpp + frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp + frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp + frontend/A64/translate/impl/simd_sha.cpp + frontend/A64/translate/impl/simd_sha512.cpp + frontend/A64/translate/impl/simd_shift_by_immediate.cpp + frontend/A64/translate/impl/simd_table_lookup.cpp + frontend/A64/translate/impl/simd_three_different.cpp + frontend/A64/translate/impl/simd_three_same.cpp + frontend/A64/translate/impl/simd_three_same_extra.cpp + frontend/A64/translate/impl/simd_two_register_misc.cpp + frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp + frontend/A64/translate/impl/sys_dc.cpp + frontend/A64/translate/impl/sys_ic.cpp + frontend/A64/translate/impl/system.cpp + frontend/A64/translate/impl/system_flag_format.cpp + frontend/A64/translate/impl/system_flag_manipulation.cpp interface/A64/a64.h interface/A64/config.h ir/opt/a64_callback_config_pass.cpp diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp index a22f296e94..6b38c41093 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,9 +7,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/arm64/a32_address_space.h" #include "dynarmic/backend/arm64/a32_core.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp index 67390a311d..e24654c7db 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include "dynarmic/backend/arm64/a32_jitstate.h" #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::Arm64 { diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h b/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h index b4fee9a4d0..978bf84ad2 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/a32_jitstate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp index 96170f08a8..7d7716783a 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,9 +7,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/arm64/a64_address_space.h" #include "dynarmic/backend/arm64/a64_core.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h b/externals/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h index 3dd422b6d4..215e6987f3 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/a64_jitstate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A64/a64_location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/abi.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/abi.cpp index 04d8ca2eaf..6d7b96379b 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/abi.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/abi.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include namespace Dynarmic::Backend::Arm64 { diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/abi.h b/externals/dynarmic/src/dynarmic/backend/arm64/abi.h index ca7c9187db..609b06cd22 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/abi.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/abi.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/common/always_false.h" @@ -62,12 +59,13 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) { } if (reg.index() == 31) { - ASSERT_FALSE("ZR not allowed in reg list"); + throw std::out_of_range("ZR not allowed in reg list"); } if (reg.index() == -1) { return RegisterList{1} << 31; } + return RegisterList{1} << reg.index(); } diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/address_space.h b/externals/dynarmic/src/dynarmic/backend/arm64/address_space.h index 25b1ab4b04..792ecf696b 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/address_space.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/address_space.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/devirtualize.h b/externals/dynarmic/src/dynarmic/backend/arm64/devirtualize.h index 14dc3809a5..c433fd0126 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/devirtualize.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/devirtualize.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include #include namespace Dynarmic::Backend::Arm64 { diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h b/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h index 801ac42818..f80f26898c 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/arm64/fastmem.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h b/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h index 3c50194689..bfc6d71f4e 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.h @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/common_types.h" +#include namespace oaknut { struct CodeGenerator; diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp index 326ab4ad00..d57a29cd85 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/exclusive_monitor.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/fastmem.h b/externals/dynarmic/src/dynarmic/backend/arm64/fastmem.h index cae05bcf23..7e14ce6d92 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/fastmem.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/fastmem.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/exception_handler.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h b/externals/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h index 3bc5683153..9e5d68bfcf 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/fpsr_manager.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace oaknut { struct CodeGenerator; diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp b/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp index 07440bd385..fedee02f07 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp +++ b/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,11 +9,11 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/arm64/abi.h" #include "dynarmic/backend/arm64/emit_context.h" diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h b/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h index bde7c8e612..5ba8332d27 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,8 +11,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/stack_layout.h b/externals/dynarmic/src/dynarmic/backend/arm64/stack_layout.h index 801b07c008..cf7f3259a9 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/stack_layout.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/stack_layout.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::Arm64 { diff --git a/externals/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h b/externals/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h index 84beda4057..73c6646139 100644 --- a/externals/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h +++ b/externals/dynarmic/src/dynarmic/backend/arm64/verbose_debugging_output.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2023 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/arm64/stack_layout.h" diff --git a/externals/dynarmic/src/dynarmic/backend/block_range_information.cpp b/externals/dynarmic/src/dynarmic/backend/block_range_information.cpp index 0e5904ae1c..ab83ce6a78 100644 --- a/externals/dynarmic/src/dynarmic/backend/block_range_information.cpp +++ b/externals/dynarmic/src/dynarmic/backend/block_range_information.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include namespace Dynarmic::Backend { diff --git a/externals/dynarmic/src/dynarmic/backend/exception_handler.h b/externals/dynarmic/src/dynarmic/backend/exception_handler.h index 173949628c..ed5c41c7b9 100644 --- a/externals/dynarmic/src/dynarmic/backend/exception_handler.h +++ b/externals/dynarmic/src/dynarmic/backend/exception_handler.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #if defined(MCL_ARCHITECTURE_X86_64) namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp b/externals/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp index 52bcf5972f..bac8d9c951 100644 --- a/externals/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp +++ b/externals/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2019 MerryMage * SPDX-License-Identifier: 0BSD @@ -18,10 +15,10 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/exception_handler.h" diff --git a/externals/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp b/externals/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp index 7695df57d2..2d6d6ea6d8 100644 --- a/externals/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp +++ b/externals/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2019 MerryMage * SPDX-License-Identifier: 0BSD @@ -16,9 +13,6 @@ # ifndef __OpenBSD__ # include # endif -# ifdef __sun__ -# include -# endif #endif #include @@ -28,9 +22,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #if defined(MCL_ARCHITECTURE_X86_64) # include "dynarmic/backend/x64/block_of_code.h" @@ -151,9 +145,9 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { #ifndef MCL_ARCHITECTURE_RISCV ucontext_t* ucontext = reinterpret_cast(raw_context); -#ifndef __OpenBSD__ +# ifndef __OpenBSD__ auto& mctx = ucontext->uc_mcontext; -#endif +# endif #endif #if defined(MCL_ARCHITECTURE_X86_64) @@ -173,9 +167,6 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { # elif defined(__OpenBSD__) # define CTX_RIP (ucontext->sc_rip) # define CTX_RSP (ucontext->sc_rsp) -# elif defined(__sun__) -# define CTX_RIP (mctx.gregs[REG_RIP]) -# define CTX_RSP (mctx.gregs[REG_RSP]) # else # error "Unknown platform" # endif diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp index efa211618b..986ae4ca79 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/backend/riscv64/a32_address_space.h" -#include "dynarmic/common/assert.h" +#include #include "dynarmic/backend/riscv64/abi.h" #include "dynarmic/backend/riscv64/emit_riscv64.h" diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp index 7ad0fd90b0..dac4d2d2a7 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,9 +7,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/riscv64/a32_address_space.h" #include "dynarmic/backend/riscv64/a32_core.h" diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp index 87eeab6b0f..70482d0a7c 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include "dynarmic/backend/riscv64/a32_jitstate.h" #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::RV64 { diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h index 2fbb5819d9..9bf6834088 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/a32_jitstate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/code_block.h b/externals/dynarmic/src/dynarmic/backend/riscv64/code_block.h index 8f98fdf01f..6ac014a51a 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/code_block.h +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/code_block.h @@ -14,26 +14,29 @@ namespace Dynarmic::Backend::RV64 { class CodeBlock { public: - explicit CodeBlock(std::size_t size) noexcept : memsize(size) { + explicit CodeBlock(std::size_t size) + : memsize(size) { mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0); + if (mem == nullptr) - ASSERT_FALSE("out of memory"); + throw std::bad_alloc{}; } - ~CodeBlock() noexcept { + ~CodeBlock() { if (mem == nullptr) return; + munmap(mem, memsize); } template - T ptr() const noexcept { + T ptr() const { static_assert(std::is_pointer_v || std::is_same_v || std::is_same_v); return reinterpret_cast(mem); } protected: - u8* mem = nullptr; + u8* mem; size_t memsize = 0; }; } // namespace Dynarmic::Backend::RV64 diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h b/externals/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h index 68d30d5e15..5cfd0212c7 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace biscuit { class Assembler; diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp b/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp index e09bd696b8..6c89d7b005 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,9 +8,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/always_false.h" diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h b/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h index e8fd471ae1..c94027d931 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -16,8 +13,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h b/externals/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h index 082e68aa6d..03c0e6f099 100644 --- a/externals/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h +++ b/externals/dynarmic/src/dynarmic/backend/riscv64/stack_layout.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2024 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::RV64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp index 43e0750d68..ce38a52c73 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,10 +11,10 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/x64/a32_jitstate.h" @@ -127,36 +124,35 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) { EmitCondPrelude(ctx); - auto const loop_all_inst = [this, &block, &ctx](auto const func) { - for (auto iter = block.begin(); iter != block.end(); ++iter) [[likely]] { - auto* inst = &*iter; - // Call the relevant Emit* member function. - switch (inst->GetOpcode()) { -#define OPCODE(name, type, ...) \ - case IR::Opcode::name: \ - A32EmitX64::Emit##name(ctx, inst); \ - break; -#define A32OPC(name, type, ...) \ - case IR::Opcode::A32##name: \ - A32EmitX64::EmitA32##name(ctx, inst);\ - break; + for (auto iter = block.begin(); iter != block.end(); ++iter) { + IR::Inst* inst = &*iter; + + // Call the relevant Emit* member function. + switch (inst->GetOpcode()) { +#define OPCODE(name, type, ...) \ + case IR::Opcode::name: \ + A32EmitX64::Emit##name(ctx, inst); \ + break; +#define A32OPC(name, type, ...) \ + case IR::Opcode::A32##name: \ + A32EmitX64::EmitA32##name(ctx, inst); \ + break; #define A64OPC(...) #include "dynarmic/ir/opcodes.inc" #undef OPCODE #undef A32OPC #undef A64OPC - default: [[unlikely]] ASSERT_FALSE("Invalid opcode: {}", inst->GetOpcode()); - } - reg_alloc.EndOfAllocScope(); - func(reg_alloc); + + default: + ASSERT_FALSE("Invalid opcode: {}", inst->GetOpcode()); + break; } - }; - if (!conf.very_verbose_debugging_output) [[likely]] { - loop_all_inst([](auto&) { /*noop*/ }); - } else [[unlikely]] { - loop_all_inst([this](auto& reg_alloc) { + + reg_alloc.EndOfAllocScope(); + + if (conf.very_verbose_debugging_output) { EmitVerboseDebuggingOutput(reg_alloc); - }); + } } reg_alloc.AssertNoMoreUses(); @@ -233,7 +229,7 @@ void A32EmitX64::GenTerminalHandlers() { terminal_handler_pop_rsb_hint = code.getCurr(); calculate_location_descriptor(); code.mov(eax, dword[r15 + offsetof(A32JitState, rsb_ptr)]); - code.dec(eax); + code.sub(eax, 1); code.and_(eax, u32(A32JitState::RSBPtrMask)); code.mov(dword[r15 + offsetof(A32JitState, rsb_ptr)], eax); code.cmp(rbx, qword[r15 + offsetof(A32JitState, rsb_location_descriptors) + rax * sizeof(u64)]); diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp index b116ec180e..d690aadade 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,10 +9,10 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/a32_emit_x64.h" #include "dynarmic/backend/x64/a32_jitstate.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp index ed5a8f9454..2e201c1cc4 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,9 +5,9 @@ #include "dynarmic/backend/x64/a32_jitstate.h" -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/nzcv_util.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h b/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h index 99510c91cf..cc13abf8e2 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/a32_jitstate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp index 47a2236a87..ad84e0ecc0 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,9 +7,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include #include @@ -201,19 +198,18 @@ void A64EmitX64::GenTerminalHandlers() { code.or_(rbx, rcx); }; - Xbyak::Label fast_dispatch_cache_miss; - Xbyak::Label rsb_cache_miss; + Xbyak::Label fast_dispatch_cache_miss, rsb_cache_miss; code.align(); terminal_handler_pop_rsb_hint = code.getCurr(); calculate_location_descriptor(); code.mov(eax, dword[r15 + offsetof(A64JitState, rsb_ptr)]); - code.dec(eax); + code.sub(eax, 1); code.and_(eax, u32(A64JitState::RSBPtrMask)); code.mov(dword[r15 + offsetof(A64JitState, rsb_ptr)], eax); code.cmp(rbx, qword[r15 + offsetof(A64JitState, rsb_location_descriptors) + rax * sizeof(u64)]); if (conf.HasOptimization(OptimizationFlag::FastDispatch)) { - code.jne(rsb_cache_miss, code.T_NEAR); + code.jne(rsb_cache_miss); } else { code.jne(code.GetReturnFromRunCodeAddress()); } diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64_memory.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64_memory.cpp index fe7dfa011f..450b16d000 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64_memory.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a64_emit_x64_memory.cpp @@ -33,13 +33,13 @@ void A64EmitX64::GenMemory128Accessors() { #ifdef _WIN32 Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCallWithReturnPointer(code, [&](Xbyak::Reg64 return_value_ptr, [[maybe_unused]] RegList args) { code.mov(code.ABI_PARAM3, code.ABI_PARAM2); - code.lea(rsp, ptr[rsp - (8 + 16 + ABI_SHADOW_SPACE)]); + code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE); code.lea(return_value_ptr, ptr[rsp + ABI_SHADOW_SPACE]); }); code.movups(xmm1, xword[code.ABI_RETURN]); code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE); #else - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCall(code); if (code.HasHostFeature(HostFeature::SSE41)) { code.movq(xmm1, code.ABI_RETURN); @@ -57,13 +57,13 @@ void A64EmitX64::GenMemory128Accessors() { code.align(); memory_write_128 = code.getCurr(); #ifdef _WIN32 - code.lea(rsp, ptr[rsp - (8 + 16 + ABI_SHADOW_SPACE)]); + code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]); code.movaps(xword[code.ABI_PARAM3], xmm1); Devirtualize<&A64::UserCallbacks::MemoryWrite128>(conf.callbacks).EmitCall(code); code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE); #else - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); if (code.HasHostFeature(HostFeature::SSE41)) { code.movq(code.ABI_PARAM3, xmm1); code.pextrq(code.ABI_PARAM4, xmm1, 1); @@ -81,7 +81,7 @@ void A64EmitX64::GenMemory128Accessors() { code.align(); memory_exclusive_write_128 = code.getCurr(); #ifdef _WIN32 - code.lea(rsp, ptr[rsp - (8 + 32 + ABI_SHADOW_SPACE)]); + code.sub(rsp, 8 + 32 + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]); code.lea(code.ABI_PARAM4, ptr[rsp + ABI_SHADOW_SPACE + 16]); code.movaps(xword[code.ABI_PARAM3], xmm1); @@ -89,7 +89,7 @@ void A64EmitX64::GenMemory128Accessors() { Devirtualize<&A64::UserCallbacks::MemoryWriteExclusive128>(conf.callbacks).EmitCall(code); code.add(rsp, 8 + 32 + ABI_SHADOW_SPACE); #else - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); if (code.HasHostFeature(HostFeature::SSE41)) { code.movq(code.ABI_PARAM3, xmm1); code.pextrq(code.ABI_PARAM4, xmm1, 1); @@ -131,8 +131,8 @@ void A64EmitX64::GenFastmemFallbacks() { {64, Devirtualize<&A64::UserCallbacks::MemoryWriteExclusive64>(conf.callbacks)}, }}; - for (auto const ordered : {false, true}) { - for (auto const vaddr_idx : idxes) { + for (bool ordered : {false, true}) { + for (int vaddr_idx : idxes) { if (vaddr_idx == 4 || vaddr_idx == 15) { continue; } diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp b/externals/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp index ddd2327395..7c0fa8d205 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h b/externals/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h index 22fd94e5c9..0929e81ec5 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/a64_jitstate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/abi.cpp b/externals/dynarmic/src/dynarmic/backend/x64/abi.cpp index e8eaddcbac..1d0b32fac9 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/abi.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/abi.cpp @@ -11,7 +11,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/x64/block_of_code.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/abi.h b/externals/dynarmic/src/dynarmic/backend/x64/abi.h index 32f2bdac67..4bddf51bad 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/abi.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/abi.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/hostloc.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp b/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp index 41603abf86..22d9868fc5 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -24,7 +21,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include @@ -66,8 +63,7 @@ public: uint8_t* alloc(size_t size) override { void* p = VirtualAlloc(nullptr, size, MEM_RESERVE, PAGE_READWRITE); if (p == nullptr) { - using Xbyak::Error; - XBYAK_THROW(Xbyak::ERR_CANT_ALLOC); + throw Xbyak::Error(Xbyak::ERR_CANT_ALLOC); } return static_cast(p); } @@ -99,8 +95,7 @@ public: void* p = mmap(nullptr, size, PROT_READ | PROT_WRITE, mode, -1, 0); if (p == MAP_FAILED) { - using Xbyak::Error; - XBYAK_THROW(Xbyak::ERR_CANT_ALLOC); + throw Xbyak::Error(Xbyak::ERR_CANT_ALLOC); } std::memcpy(p, &size, sizeof(size_t)); return static_cast(p) + DYNARMIC_PAGE_SIZE; @@ -519,8 +514,7 @@ size_t BlockOfCode::GetTotalCodeSize() const { void* BlockOfCode::AllocateFromCodeSpace(size_t alloc_size) { if (size_ + alloc_size >= maxSize_) { - using Xbyak::Error; - XBYAK_THROW(Xbyak::ERR_CODE_IS_TOO_BIG); + throw Xbyak::Error(Xbyak::ERR_CODE_IS_TOO_BIG); } EnsureMemoryCommitted(alloc_size); diff --git a/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.h b/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.h index 4cc8663e11..6a31d13857 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/block_of_code.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,7 +11,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/x64/callback.h b/externals/dynarmic/src/dynarmic/backend/x64/callback.h index 3254eea66c..716555daed 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/callback.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/callback.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp b/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp index 7dbd46bc2a..ba003262b3 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include "dynarmic/backend/x64/block_of_code.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.h b/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.h index 8115dcff26..dcf1e9cdc7 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/constant_pool.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/x64/constants.h b/externals/dynarmic/src/dynarmic/backend/x64/constants.h index 65c5a09a53..f817324142 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/constants.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/constants.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/rounding_mode.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/devirtualize.h b/externals/dynarmic/src/dynarmic/backend/x64/devirtualize.h index 318a702194..778536a3bb 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/devirtualize.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/devirtualize.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/x64/callback.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp index d428199585..8bd9102d0d 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,10 +7,10 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/x64/block_of_code.h" @@ -107,7 +104,7 @@ void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, I } void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc) { - code.lea(rsp, ptr[rsp - sizeof(RegisterData)]); + code.sub(rsp, sizeof(RegisterData)); code.stmxcsr(dword[rsp + offsetof(RegisterData, mxcsr)]); for (int i = 0; i < 16; i++) { if (rsp.getIdx() == i) { @@ -226,7 +223,7 @@ void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg value = ctx.reg_alloc.UseGpr(args[0]).changeBit(bitsize); code.test(value, value); code.lahf(); - code.xor_(al, al); + code.mov(al, 0); ctx.reg_alloc.DefineValue(inst, nzcv); } @@ -273,6 +270,7 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) { code.shr(nzcv, 28); code.imul(nzcv, nzcv, NZCV::to_x64_multiplier); code.and_(nzcv, NZCV::x64_mask); + ctx.reg_alloc.DefineValue(inst, nzcv); } } @@ -333,8 +331,10 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) { code.jle(pass); break; default: - UNREACHABLE(); + ASSERT_MSG(false, "Unknown cond {}", static_cast(cond)); + break; } + return pass; } diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp index 2ec9bce068..9430f0726b 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_aes.cpp @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp index 4128ef1721..98197c2db3 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,8 +6,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/emit_x64.h" @@ -995,6 +992,7 @@ static void EmitAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bit code.seto(overflow); ctx.reg_alloc.DefineValue(overflow_inst, overflow); } + ctx.reg_alloc.DefineValue(inst, result); } diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp index 63b9659618..182c887538 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,14 +7,14 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include #include #include #include #include -#include "dynarmic/common/common_types.h" +#include #include #include @@ -36,23 +33,6 @@ #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" -#define FCODE(NAME) \ - [&code](auto... args) { \ - if constexpr (fsize == 32) { \ - code.NAME##s(args...); \ - } else { \ - code.NAME##d(args...); \ - } \ - } -#define ICODE(NAME) \ - [&code](auto... args) { \ - if constexpr (fsize == 32) { \ - code.NAME##d(args...); \ - } else { \ - code.NAME##q(args...); \ - } \ - } - namespace Dynarmic::Backend::X64 { using namespace Xbyak::util; @@ -80,6 +60,23 @@ constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double constexpr u64 f64_max_s64_lim = 0x43e0000000000000u; // 2^63 as a double (actual maximum unrepresentable) +#define FCODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##s(args...); \ + } else { \ + code.NAME##d(args...); \ + } \ + } +#define ICODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##d(args...); \ + } else { \ + code.NAME##q(args...); \ + } \ + } + template void ForceDenormalsToZero(BlockOfCode& code, std::initializer_list to_daz) { if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) { @@ -476,7 +473,7 @@ static void EmitFPMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { } template -static inline void EmitFPMinMaxNumeric(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) noexcept { +static void EmitFPMinMaxNumeric(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { using FPT = mcl::unsigned_integer_of_size; constexpr FPT default_nan = FP::FPInfo::DefaultNaN(); @@ -704,14 +701,15 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { // x64 rounds before flushing to zero // AArch64 rounds after flushing to zero // This difference of behaviour is noticable if something would round to a smallest normalized number - code.lea(rsp, ptr[rsp - 8]); + + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); code.movq(code.ABI_PARAM1, operand1); code.movq(code.ABI_PARAM2, operand2); code.movq(code.ABI_PARAM3, operand3); code.mov(code.ABI_PARAM4.cvt32(), ctx.FPCR().Value()); #ifdef _WIN32 - code.lea(rsp, ptr[rsp - (16 + ABI_SHADOW_SPACE)]); + code.sub(rsp, 16 + ABI_SHADOW_SPACE); code.lea(rax, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); code.mov(qword[rsp + ABI_SHADOW_SPACE], rax); code.CallFunction(fallback_fn); @@ -737,13 +735,13 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { code.vmovaps(xmm0, code.Const(xword, FP::FPInfo::mantissa_msb)); FCODE(ucomis)(operand2, operand3); - code.jp(has_nan, code.T_NEAR); + code.jp(has_nan); FCODE(ucomis)(operand1, operand1); - code.jnp(indeterminate, code.T_NEAR); + code.jnp(indeterminate); // AArch64 specifically emits a default NaN for the case when the addend is a QNaN and the two other arguments are {inf, zero} code.ptest(operand1, xmm0); - code.jz(op1_snan, code.T_NEAR); + code.jz(op1_snan); FCODE(vmuls)(xmm0, operand2, operand3); // check if {op2, op3} are {inf, zero}/{zero, inf} FCODE(ucomis)(xmm0, xmm0); code.jnp(*end); @@ -755,10 +753,10 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { code.L(has_nan); FCODE(ucomis)(operand1, operand1); - code.jnp(op1_done, code.T_NEAR); + code.jnp(op1_done); code.movaps(result, operand1); // this is done because of NaN behavior of vfmadd231s (priority of op2, op3, op1) code.ptest(operand1, xmm0); - code.jnz(op1_done, code.T_NEAR); + code.jnz(op1_done); code.L(op1_snan); code.vorps(result, operand1, xmm0); code.jmp(*end); @@ -776,9 +774,9 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { code.L(op2_done); FCODE(ucomis)(operand3, operand3); - code.jnp(op3_done, code.T_NEAR); + code.jnp(op3_done); code.ptest(operand3, xmm0); - code.jnz(op3_done, code.T_NEAR); + code.jnz(op3_done); code.vorps(result, operand3, xmm0); code.jmp(*end); code.L(op3_done); @@ -1021,7 +1019,7 @@ static void EmitFPRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*fallback); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); code.movq(code.ABI_PARAM1, operand1); code.movq(code.ABI_PARAM2, operand2); @@ -1206,9 +1204,9 @@ static void EmitFPRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i } // a > 0 && a < 0x00800000; - code.dec(tmp); + code.sub(tmp, 1); code.cmp(tmp, 0x007FFFFF); - code.jb(fallback, code.T_NEAR); //within -127,128 + code.jb(fallback); needs_fallback = true; } @@ -1237,17 +1235,17 @@ static void EmitFPRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i code.ucomisd(value, result); if (ctx.FPCR().DN()) { - code.jc(default_nan, code.T_NEAR); - code.je(zero, code.T_NEAR); + code.jc(default_nan); + code.je(zero); } else { - code.jp(nan, code.T_NEAR); - code.je(zero, code.T_NEAR); - code.jc(default_nan, code.T_NEAR); + code.jp(nan); + code.je(zero); + code.jc(default_nan); } if (!ctx.FPCR().FZ()) { needs_fallback = true; - code.jmp(fallback, code.T_NEAR); + code.jmp(fallback); } else { // result = 0 code.jmp(*end, code.T_NEAR); @@ -1280,7 +1278,7 @@ static void EmitFPRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i code.L(fallback); if (needs_fallback) { - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); code.movq(code.ABI_PARAM1, operand); code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR().Value()); @@ -1363,7 +1361,7 @@ static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*fallback); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); code.movq(code.ABI_PARAM1, operand1); code.movq(code.ABI_PARAM2, operand2); @@ -2134,6 +2132,3 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } } // namespace Dynarmic::Backend::X64 - -#undef FCODE -#undef ICODE diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h index b25b33101c..c99980d617 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h @@ -161,7 +161,8 @@ template<> template<> [[maybe_unused]] Xbyak::RegExp EmitFastmemVAddr(BlockOfCode& code, A64EmitContext& ctx, Xbyak::Label& abort, Xbyak::Reg64 vaddr, bool& require_abort_handling, std::optional tmp) { - auto const unused_top_bits = 64 - ctx.conf.fastmem_address_space_bits; + const size_t unused_top_bits = 64 - ctx.conf.fastmem_address_space_bits; + if (unused_top_bits == 0) { return r13 + vaddr; } else if (ctx.conf.silently_mirror_fastmem) { @@ -305,7 +306,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int code.L(loop); code.lock(); code.cmpxchg16b(xword[addr]); - code.jnz(loop, code.T_NEAR); + code.jnz(loop); break; } default: @@ -372,7 +373,7 @@ void EmitExclusiveTestAndClear(BlockOfCode& code, const UserConfig& conf, Xbyak: Xbyak::Label ok; code.mov(pointer, mcl::bit_cast(GetExclusiveMonitorAddressPointer(conf.global_monitor, processor_index))); code.cmp(qword[pointer], vaddr); - code.jne(ok, code.T_NEAR); + code.jne(ok); code.mov(qword[pointer], tmp); code.L(ok); } diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp index d36a75426a..24fb895b61 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,9 +5,9 @@ #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/backend/x64/block_of_code.h" diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp index e9b8866b52..5d5ea17422 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,11 +9,11 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include #include -#include "dynarmic/common/common_types.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp index b24120c346..b8aa3eb653 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include #include @@ -36,6 +33,13 @@ #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" +namespace Dynarmic::Backend::X64 { + +using namespace Xbyak::util; +namespace mp = mcl::mp; + +namespace { + #define FCODE(NAME) \ [&code](auto... args) { \ if constexpr (fsize == 32) { \ @@ -53,13 +57,6 @@ } \ } -namespace Dynarmic::Backend::X64 { - -using namespace Xbyak::util; -namespace mp = mcl::mp; - -namespace { - template void MaybeStandardFPSCRValue(BlockOfCode& code, EmitContext& ctx, bool fpcr_controlled, Lambda lambda) { const bool switch_mxcsr = ctx.FPCR(fpcr_controlled) != ctx.FPCR(); @@ -125,11 +122,11 @@ void HandleNaNs(BlockOfCode& code, EmitContext& ctx, bool fpcr_controlled, std:: const Xbyak::Xmm result = xmms[0]; - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); const size_t stack_space = xmms.size() * 16; - code.lea(rsp, ptr[rsp - static_cast(stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, static_cast(stack_space + ABI_SHADOW_SPACE)); for (size_t i = 0; i < xmms.size(); ++i) { code.movaps(xword[rsp + ABI_SHADOW_SPACE + i * 16], xmms[i]); } @@ -446,7 +443,7 @@ void EmitTwoOpFallbackWithoutRegAlloc(BlockOfCode& code, EmitContext& ctx, Xbyak const u32 fpcr = ctx.FPCR(fpcr_controlled).Value(); constexpr u32 stack_space = 2 * 16; - code.lea(rsp, ptr[rsp - (stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 0 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); code.mov(code.ABI_PARAM3.cvt32(), fpcr); @@ -482,7 +479,7 @@ void EmitThreeOpFallbackWithoutRegAlloc(BlockOfCode& code, EmitContext& ctx, Xby #ifdef _WIN32 constexpr u32 stack_space = 4 * 16; - code.lea(rsp, ptr[rsp - (stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 2 * 16]); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE + 3 * 16]); @@ -491,7 +488,7 @@ void EmitThreeOpFallbackWithoutRegAlloc(BlockOfCode& code, EmitContext& ctx, Xby code.mov(qword[rsp + ABI_SHADOW_SPACE + 0], rax); #else constexpr u32 stack_space = 3 * 16; - code.lea(rsp, ptr[rsp - (stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 0 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE + 2 * 16]); @@ -539,7 +536,7 @@ void EmitFourOpFallbackWithoutRegAlloc(BlockOfCode& code, EmitContext& ctx, Xbya #ifdef _WIN32 constexpr u32 stack_space = 5 * 16; - code.lea(rsp, ptr[rsp - (stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 2 * 16]); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE + 3 * 16]); @@ -549,7 +546,7 @@ void EmitFourOpFallbackWithoutRegAlloc(BlockOfCode& code, EmitContext& ctx, Xbya code.mov(qword[rsp + ABI_SHADOW_SPACE + 8], rax); #else constexpr u32 stack_space = 4 * 16; - code.lea(rsp, ptr[rsp - (stack_space + ABI_SHADOW_SPACE)]); + code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 0 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE + 2 * 16]); @@ -1374,7 +1371,7 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*fallback); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); if (needs_rounding_correction && needs_nan_correction) { EmitFourOpFallbackWithoutRegAlloc(code, ctx, result, xmm_a, xmm_b, xmm_c, EmitFPVectorMulAddFallback, fpcr_controlled); @@ -1638,7 +1635,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*fallback); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn, fpcr_controlled); ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); @@ -1815,7 +1812,7 @@ static void EmitRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*bad_values); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); EmitTwoOpFallbackWithoutRegAlloc(code, ctx, result, operand, fallback_fn, fpcr_controlled); ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); @@ -1901,7 +1898,7 @@ static void EmitRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in ctx.deferred_emits.emplace_back([=, &code, &ctx] { code.L(*fallback); - code.lea(rsp, ptr[rsp - 8]); + code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn, fpcr_controlled); ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); @@ -2183,6 +2180,3 @@ void EmitX64::EmitFPVectorToUnsignedFixed64(EmitContext& ctx, IR::Inst* inst) { } } // namespace Dynarmic::Backend::X64 - -#undef FCODE -#undef ICODE diff --git a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp index 88bd41a47e..fb30549fb0 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/constants.h" @@ -341,6 +338,3 @@ void EmitX64::EmitVectorUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) } } // namespace Dynarmic::Backend::X64 - -#undef FCODE -#undef ICODE diff --git a/externals/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp b/externals/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp index 95eacaae9b..a7f964337a 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,9 +9,9 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/exception_handler.h" #include "dynarmic/backend/x64/block_of_code.h" @@ -189,7 +186,7 @@ struct ExceptionHandler::Impl final { code.cmp(code.rax, static_cast(code.GetTotalCodeSize())); code.ja(exception_handler_without_cb); - code.lea(code.rsp, code.ptr[code.rsp - 8]); + code.sub(code.rsp, 8); code.mov(code.ABI_PARAM1, mcl::bit_cast(&cb)); code.mov(code.ABI_PARAM2, code.ABI_PARAM3); code.CallLambda( diff --git a/externals/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp b/externals/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp index 09ef60205f..984b67bb02 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/exclusive_monitor.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/host_feature.h b/externals/dynarmic/src/dynarmic/backend/x64/host_feature.h index 7246ed18d4..8e3b14c7bb 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/host_feature.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/host_feature.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/hostloc.h b/externals/dynarmic/src/dynarmic/backend/x64/hostloc.h index 1b27edbdee..d8de3931da 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/hostloc.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/hostloc.h @@ -1,14 +1,11 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD */ #pragma once -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/nzcv_util.h b/externals/dynarmic/src/dynarmic/backend/x64/nzcv_util.h index 1ee0ed4329..3a70cf4f0b 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/nzcv_util.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/nzcv_util.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64::NZCV { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/oparg.h b/externals/dynarmic/src/dynarmic/backend/x64/oparg.h index 4e165b9df9..70c60dfb15 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/oparg.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/oparg.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/assert.h" +#include #include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp b/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp index ab3172a7f3..a0ee8ae9ed 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp +++ b/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include @@ -418,54 +415,21 @@ void RegAlloc::ReleaseStackSpace(const size_t stack_space) noexcept { } HostLoc RegAlloc::SelectARegister(const boost::container::static_vector& desired_locations) const noexcept { - // TODO(lizzie): Overspill causes issues (reads to 0 and such) on some games, I need to make a testbench - // to later track this down - however I just modified the LRU algo so it prefers empty registers first - // we need to test high register pressure (and spills, maybe 32 regs?) + boost::container::static_vector candidates = desired_locations; //Who let someone copy an ENTIRE VECTOR here? + + // Find all locations that have not been allocated.. + const auto allocated_locs = std::partition(candidates.begin(), candidates.end(), [this](auto loc) noexcept { + return !this->LocInfo(loc).IsLocked(); + }); + candidates.erase(allocated_locs, candidates.end()); + ASSERT_MSG(!candidates.empty(), "All candidate registers have already been allocated"); // Selects the best location out of the available locations. - // NOTE: Using last is BAD because new REX prefix for each insn using the last regs // TODO: Actually do LRU or something. Currently we just try to pick something without a value if possible. - auto min_lru_counter = size_t(-1); - auto it_candidate = desired_locations.cend(); //default fallback if everything fails - auto it_rex_candidate = desired_locations.cend(); - auto it_empty_candidate = desired_locations.cend(); - for (auto it = desired_locations.cbegin(); it != desired_locations.cend(); it++) { - auto const& loc_info = LocInfo(*it); - // Abstain from using upper registers unless absolutely nescesary - if (loc_info.IsLocked()) { - // skip, not suitable for allocation - } else { - if (loc_info.lru_counter < min_lru_counter) { - if (loc_info.IsEmpty()) - it_empty_candidate = it; - // Otherwise a "quasi"-LRU - min_lru_counter = loc_info.lru_counter; - if (*it >= HostLoc::R8 && *it <= HostLoc::R15) { - it_rex_candidate = it; - } else { - it_candidate = it; - } - if (min_lru_counter == 0) - break; //early exit - } - // only if not assigned (i.e for failcase of all LRU=0) - if (it_empty_candidate == desired_locations.cend() && loc_info.IsEmpty()) - it_empty_candidate = it; - } - } - // Final resolution goes as follows: - // 1 => Try an empty candidate - // 2 => Try normal candidate (no REX prefix) - // 3 => Try using a REX prefixed one - // We avoid using REX-addressable registers because they add +1 REX prefix which - // do we really need? The trade-off may not be worth it. - auto const it_final = it_empty_candidate != desired_locations.cend() - ? it_empty_candidate : it_candidate != desired_locations.cend() - ? it_candidate : it_rex_candidate; - ASSERT_MSG(it_final != desired_locations.cend(), "All candidate registers have already been allocated"); - // Evil magic - increment LRU counter (will wrap at 256) - const_cast(this)->LocInfo(*it_final).lru_counter++; - return *it_final; + auto const it = std::find_if(candidates.begin(), candidates.end(), [this](auto const loc) noexcept { + return this->LocInfo(loc).IsEmpty(); + }); + return it != candidates.end() ? *it : candidates.front(); } void RegAlloc::DefineValueImpl(IR::Inst* def_inst, HostLoc host_loc) noexcept { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.h b/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.h index f9b6477b60..599aab12a8 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/reg_alloc.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include #include @@ -95,8 +92,8 @@ private: uint8_t max_bit_width = 0; //Valid values: 1,2,4,8,16,32,128 bool is_scratch : 1 = false; //1 bool is_set_last_use : 1 = false; //1 - alignas(16) uint8_t lru_counter = 0; //1 - friend class RegAlloc; + + alignas(16) char padding; }; static_assert(sizeof(HostLocInfo) == 64); diff --git a/externals/dynarmic/src/dynarmic/backend/x64/stack_layout.h b/externals/dynarmic/src/dynarmic/backend/x64/stack_layout.h index 50737f12eb..7e6799f1cf 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/stack_layout.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/stack_layout.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/externals/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h b/externals/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h index 68d0ccff24..70183a6073 100644 --- a/externals/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h +++ b/externals/dynarmic/src/dynarmic/backend/x64/verbose_debugging_output.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2023 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/backend/x64/stack_layout.h" diff --git a/externals/dynarmic/src/dynarmic/common/atomic.h b/externals/dynarmic/src/dynarmic/common/atomic.h index 966921eb9a..34042d3802 100644 --- a/externals/dynarmic/src/dynarmic/common/atomic.h +++ b/externals/dynarmic/src/dynarmic/common/atomic.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Atomic { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/aes.cpp b/externals/dynarmic/src/dynarmic/common/crypto/aes.cpp index c72481fbe3..c431758e57 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/aes.cpp +++ b/externals/dynarmic/src/dynarmic/common/crypto/aes.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::AES { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/aes.h b/externals/dynarmic/src/dynarmic/common/crypto/aes.h index f5d68fe166..fa6d5a81b3 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/aes.h +++ b/externals/dynarmic/src/dynarmic/common/crypto/aes.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::AES { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/crc32.cpp b/externals/dynarmic/src/dynarmic/common/crypto/crc32.cpp index c2821fa2c3..c00385078b 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/crc32.cpp +++ b/externals/dynarmic/src/dynarmic/common/crypto/crc32.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::CRC32 { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/crc32.h b/externals/dynarmic/src/dynarmic/common/crypto/crc32.h index 391bd8074b..30942327d4 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/crc32.h +++ b/externals/dynarmic/src/dynarmic/common/crypto/crc32.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::CRC32 { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/sm4.cpp b/externals/dynarmic/src/dynarmic/common/crypto/sm4.cpp index d775e1bf6d..5743e5be9a 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/sm4.cpp +++ b/externals/dynarmic/src/dynarmic/common/crypto/sm4.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::SM4 { diff --git a/externals/dynarmic/src/dynarmic/common/crypto/sm4.h b/externals/dynarmic/src/dynarmic/common/crypto/sm4.h index af7a67f871..417e9b9263 100644 --- a/externals/dynarmic/src/dynarmic/common/crypto/sm4.h +++ b/externals/dynarmic/src/dynarmic/common/crypto/sm4.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::SM4 { diff --git a/externals/dynarmic/src/dynarmic/common/fp/fpcr.h b/externals/dynarmic/src/dynarmic/common/fp/fpcr.h index 803c9cb2a4..287f6d2889 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/fpcr.h +++ b/externals/dynarmic/src/dynarmic/common/fp/fpcr.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,9 +7,9 @@ #include -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/rounding_mode.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/fpsr.h b/externals/dynarmic/src/dynarmic/common/fp/fpsr.h index 9308132879..fba58ebbb7 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/fpsr.h +++ b/externals/dynarmic/src/dynarmic/common/fp/fpsr.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/externals/dynarmic/src/dynarmic/common/fp/info.h b/externals/dynarmic/src/dynarmic/common/fp/info.h index 3969843f0f..8cc2d29de4 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/info.h +++ b/externals/dynarmic/src/dynarmic/common/fp/info.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/externals/dynarmic/src/dynarmic/common/fp/mantissa_util.h b/externals/dynarmic/src/dynarmic/common/fp/mantissa_util.h index 3999f97c27..31be52f761 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/mantissa_util.h +++ b/externals/dynarmic/src/dynarmic/common/fp/mantissa_util.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp index 906aa781a1..85f1eaf899 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPConvert.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2019 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp index 6990b135f6..f97f88de17 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPMulAdd.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/common/fp/op/FPMulAdd.h" -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp index 6b2d43e1ce..ed28bcc5cc 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/common/fp/op/FPRSqrtEstimate.h" -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp index edab4bf147..1fd4b924b2 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipEstimate.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,8 +7,8 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp index e932e02803..171b94e96e 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPRecipExponent.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include "dynarmic/common/fp/op/FPRecipExponent.h" #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp index 198a71c807..7325909075 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,9 +5,9 @@ #include "dynarmic/common/fp/op/FPRoundInt.h" -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h b/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h index 1eb2bd8877..e326627ce1 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp b/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp index 8e3474952a..b1a57d3104 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,10 +6,10 @@ #include "dynarmic/common/fp/op/FPToFixed.h" #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h b/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h index 6e19607d51..53a952836e 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h +++ b/externals/dynarmic/src/dynarmic/common/fp/op/FPToFixed.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/externals/dynarmic/src/dynarmic/common/fp/process_exception.cpp b/externals/dynarmic/src/dynarmic/common/fp/process_exception.cpp index 4f34ee0f34..a97e0ec820 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/process_exception.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/process_exception.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/common/fp/process_exception.h" -#include "dynarmic/common/assert.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/process_nan.cpp b/externals/dynarmic/src/dynarmic/common/fp/process_nan.cpp index ff1b09f4ba..516b92adb6 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/process_nan.cpp +++ b/externals/dynarmic/src/dynarmic/common/fp/process_nan.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/common/fp/fpcr.h" diff --git a/externals/dynarmic/src/dynarmic/common/fp/unpacked.h b/externals/dynarmic/src/dynarmic/common/fp/unpacked.h index 49dca74304..77f33d8966 100644 --- a/externals/dynarmic/src/dynarmic/common/fp/unpacked.h +++ b/externals/dynarmic/src/dynarmic/common/fp/unpacked.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" diff --git a/externals/dynarmic/src/dynarmic/common/llvm_disassemble.cpp b/externals/dynarmic/src/dynarmic/common/llvm_disassemble.cpp index 31d55c134c..636ee3a250 100644 --- a/externals/dynarmic/src/dynarmic/common/llvm_disassemble.cpp +++ b/externals/dynarmic/src/dynarmic/common/llvm_disassemble.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -15,9 +12,9 @@ # include #endif -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/llvm_disassemble.h" diff --git a/externals/dynarmic/src/dynarmic/common/llvm_disassemble.h b/externals/dynarmic/src/dynarmic/common/llvm_disassemble.h index 226b742ec5..56de791a56 100644 --- a/externals/dynarmic/src/dynarmic/common/llvm_disassemble.h +++ b/externals/dynarmic/src/dynarmic/common/llvm_disassemble.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/externals/dynarmic/src/dynarmic/common/math_util.h b/externals/dynarmic/src/dynarmic/common/math_util.h index 8915100ae4..5c1f784c89 100644 --- a/externals/dynarmic/src/dynarmic/common/math_util.h +++ b/externals/dynarmic/src/dynarmic/common/math_util.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/externals/dynarmic/src/dynarmic/common/safe_ops.h b/externals/dynarmic/src/dynarmic/common/safe_ops.h index f494bdb24b..aef3134762 100644 --- a/externals/dynarmic/src/dynarmic/common/safe_ops.h +++ b/externals/dynarmic/src/dynarmic/common/safe_ops.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/u128.h" diff --git a/externals/dynarmic/src/dynarmic/common/u128.cpp b/externals/dynarmic/src/dynarmic/common/u128.cpp index fb7de7a495..dd78ac97ef 100644 --- a/externals/dynarmic/src/dynarmic/common/u128.cpp +++ b/externals/dynarmic/src/dynarmic/common/u128.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/common/u128.h" -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/common/u128.h b/externals/dynarmic/src/dynarmic/common/u128.h index 9ab4aa0bd5..f6df1ae6cc 100644 --- a/externals/dynarmic/src/dynarmic/common/u128.h +++ b/externals/dynarmic/src/dynarmic/common/u128.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/common/x64_disassemble.cpp b/externals/dynarmic/src/dynarmic/common/x64_disassemble.cpp index af37c93c02..854de23a77 100644 --- a/externals/dynarmic/src/dynarmic/common/x64_disassemble.cpp +++ b/externals/dynarmic/src/dynarmic/common/x64_disassemble.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/externals/dynarmic/src/dynarmic/common/x64_disassemble.h b/externals/dynarmic/src/dynarmic/common/x64_disassemble.h index 0f56464175..03c511bfda 100644 --- a/externals/dynarmic/src/dynarmic/common/x64_disassemble.h +++ b/externals/dynarmic/src/dynarmic/common/x64_disassemble.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/FPSCR.h b/externals/dynarmic/src/dynarmic/frontend/A32/FPSCR.h index 7a4c738e9e..28414e9fa1 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/FPSCR.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/FPSCR.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/rounding_mode.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/ITState.h b/externals/dynarmic/src/dynarmic/frontend/A32/ITState.h index eeddaeb6b5..ae69fa1e3f 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/ITState.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/ITState.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2019 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/ir/cond.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/PSR.h b/externals/dynarmic/src/dynarmic/frontend/A32/PSR.h index 328fdb17c0..9af78eaae5 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/PSR.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/PSR.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A32/ITState.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp index 396ab938f7..343e521aba 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/frontend/A32/a32_ir_emitter.h" -#include "dynarmic/common/assert.h" +#include #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/interface/A32/arch_version.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h b/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h index 0492b872ec..9fde4f8775 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/ir/ir_emitter.h" @@ -18,7 +15,7 @@ namespace Dynarmic::A32 { -enum class ArchVersion : std::uint8_t; +enum class ArchVersion; enum class CoprocReg; enum class Exception; enum class ExtReg; @@ -30,11 +27,12 @@ enum class Reg; * The user of this class updates `current_location` as appropriate. */ class IREmitter : public IR::IREmitter { - IR::U64 ImmCurrentLocationDescriptor(); public: IREmitter(IR::Block& block, LocationDescriptor descriptor, ArchVersion arch_version) : IR::IREmitter(block), current_location(descriptor), arch_version(arch_version) {} - + + LocationDescriptor current_location; + size_t ArchVersion() const; u32 PC() const; @@ -109,9 +107,10 @@ public: IR::U64 CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm); void CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option); void CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option); -public: - LocationDescriptor current_location; + +private: enum ArchVersion arch_version; + IR::U64 ImmCurrentLocationDescriptor(); }; } // namespace Dynarmic::A32 diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h b/externals/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h index cd850d0087..c53e75d4b7 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/a32_location_descriptor.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A32/FPSCR.h" #include "dynarmic/frontend/A32/ITState.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/a32_types.h b/externals/dynarmic/src/dynarmic/frontend/A32/a32_types.h index 5afd82f77f..6f56bea51a 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/a32_types.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/a32_types.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,8 +9,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/interface/A32/coprocessor_util.h" #include "dynarmic/ir/cond.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h index 0257c28ddb..16ae52e13a 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/arm.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -16,7 +13,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" @@ -36,11 +33,13 @@ inline size_t ToFastLookupIndexArm(u32 instruction) { } // namespace detail template -constexpr ArmDecodeTable GetArmDecodeTable() { +ArmDecodeTable GetArmDecodeTable() { std::vector> list = { + #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(ArmMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)), #include "./arm.inc" #undef INST + }; // If a matcher has more bits in its mask it is more specific, so it should come first. @@ -63,10 +62,9 @@ constexpr ArmDecodeTable GetArmDecodeTable() { template std::optional>> DecodeArm(u32 instruction) { - alignas(64) static const auto table = GetArmDecodeTable(); - const auto matches_instruction = [instruction](const auto& matcher) { - return matcher.Matches(instruction); - }; + static const auto table = GetArmDecodeTable(); + + const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; const auto& subtable = table[detail::ToFastLookupIndexArm(instruction)]; auto iter = std::find_if(subtable.begin(), subtable.end(), matches_instruction); diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h index f2e206695b..cfcd28c6e6 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/asimd.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -15,7 +12,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h index 8073ee5d47..6a4275f726 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb16.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h index 86a4d767a7..f3f4b3b9ee 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/thumb32.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h index 5fcacd2bda..f79a859bf7 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/decoder/vfp.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2032 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h b/externals/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h index 1b16584dcf..6a61afdefa 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::A32 { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.cpp index 2e69927ace..97a7f11adf 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.cpp @@ -25,51 +25,3 @@ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, } } // namespace Dynarmic::A32 - -// ls -l | awk '{print "#include \"dynarmic/frontend/A32/translate/impl/" $9 "\""}' -#include "dynarmic/frontend/A32/translate/impl/a32_branch.cpp" -#include "dynarmic/frontend/A32/translate/impl/a32_crc32.cpp" -#include "dynarmic/frontend/A32/translate/impl/a32_exception_generating.cpp" -#include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp" -//#include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_misc.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp" -#include "dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp" -#include "dynarmic/frontend/A32/translate/impl/barrier.cpp" -#include "dynarmic/frontend/A32/translate/impl/coprocessor.cpp" -#include "dynarmic/frontend/A32/translate/impl/data_processing.cpp" -#include "dynarmic/frontend/A32/translate/impl/divide.cpp" -#include "dynarmic/frontend/A32/translate/impl/extension.cpp" -#include "dynarmic/frontend/A32/translate/impl/hint.cpp" -#include "dynarmic/frontend/A32/translate/impl/load_store.cpp" -#include "dynarmic/frontend/A32/translate/impl/misc.cpp" -#include "dynarmic/frontend/A32/translate/impl/multiply.cpp" -#include "dynarmic/frontend/A32/translate/impl/packing.cpp" -#include "dynarmic/frontend/A32/translate/impl/parallel.cpp" -#include "dynarmic/frontend/A32/translate/impl/reversal.cpp" -#include "dynarmic/frontend/A32/translate/impl/saturated.cpp" -#include "dynarmic/frontend/A32/translate/impl/status_register_access.cpp" -#include "dynarmic/frontend/A32/translate/impl/synchronization.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb16.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_branch.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_control.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_coprocessor.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_long_multiply.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_misc.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp" -#include "dynarmic/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp" -#include "dynarmic/frontend/A32/translate/impl/vfp.cpp" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h b/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h index df0b86e9ff..0f2c3a121f 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/a32_translate.h @@ -1,13 +1,10 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD */ #pragma once -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/interface/A32/arch_version.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp index 725418ec04..2675657483 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,8 +7,8 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/frontend/A32/a32_ir_emitter.h" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h b/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h index ab52dd7198..27e1c98da7 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { enum class Cond; diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp index 64040124fe..276f8384e7 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,16 +5,12 @@ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/common/assert.h" +#include #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { -bool TranslatorVisitor::arm_NOP() { - return true; -} - bool TranslatorVisitor::ArmConditionPassed(Cond cond) { return IsConditionPassed(*this, cond); } diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h index 0a3cab3c12..44ac24503c 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #pragma once -#include "dynarmic/common/assert.h" +#include #include #include @@ -261,7 +258,7 @@ struct TranslatorVisitor final { bool arm_CLZ(Cond cond, Reg d, Reg m); bool arm_MOVT(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12); bool arm_MOVW(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12); - bool arm_NOP(); + bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); bool arm_SBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, Reg n); bool arm_SEL(Cond cond, Reg n, Reg d, Reg m); diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp index 9d73e7d4ae..e30c438eff 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp index 459cbfea06..94e3e841e8 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp index da8f43f2fb..a69f39bfb6 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp @@ -6,7 +6,6 @@ #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { namespace { @@ -18,6 +17,11 @@ enum class Comparison { AbsoluteGT, }; +enum class AccumulateBehavior { + None, + Accumulate, +}; + enum class WidenBehaviour { Second, Both, diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index ddae1f420b..62b9af55a5 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -8,11 +8,10 @@ #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { namespace { -enum class ComparisonATRM { +enum class Comparison { EQ, GE, GT, @@ -20,7 +19,7 @@ enum class ComparisonATRM { LT, }; -bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm, ComparisonATRM type) { +bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm, Comparison type) { if (sz == 0b11 || (F && sz != 0b10)) { return v.UndefinedInstruction(); } @@ -37,15 +36,15 @@ bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, if (F) { switch (type) { - case ComparisonATRM::EQ: + case Comparison::EQ: return v.ir.FPVectorEqual(32, reg_m, zero, false); - case ComparisonATRM::GE: + case Comparison::GE: return v.ir.FPVectorGreaterEqual(32, reg_m, zero, false); - case ComparisonATRM::GT: + case Comparison::GT: return v.ir.FPVectorGreater(32, reg_m, zero, false); - case ComparisonATRM::LE: + case Comparison::LE: return v.ir.FPVectorGreaterEqual(32, zero, reg_m, false); - case ComparisonATRM::LT: + case Comparison::LT: return v.ir.FPVectorGreater(32, zero, reg_m, false); } @@ -68,6 +67,11 @@ bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, return true; } +enum class AccumulateBehavior { + None, + Accumulate, +}; + bool PairedAddOperation(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm, AccumulateBehavior accumulate) { if (sz == 0b11) { return v.UndefinedInstruction(); @@ -381,23 +385,23 @@ bool TranslatorVisitor::asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M } bool TranslatorVisitor::asimd_VCGT_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, ComparisonATRM::GT); + return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::GT); } bool TranslatorVisitor::asimd_VCGE_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, ComparisonATRM::GE); + return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::GE); } bool TranslatorVisitor::asimd_VCEQ_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, ComparisonATRM::EQ); + return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::EQ); } bool TranslatorVisitor::asimd_VCLE_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, ComparisonATRM::LE); + return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::LE); } bool TranslatorVisitor::asimd_VCLT_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, ComparisonATRM::LT); + return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::LT); } bool TranslatorVisitor::asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp index 4d6855f1ed..8d1876a05d 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index 27e94628a8..b7300f91e4 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" +#include #include #include @@ -19,7 +16,7 @@ enum class Accumulating { Accumulate }; -enum class RoundingATRS { +enum class Rounding { None, Round, }; @@ -35,7 +32,7 @@ enum class Signedness { Unsigned }; -IR::U128 PerformRoundingATRSCorrection(TranslatorVisitor& v, size_t esize, u64 round_value, IR::U128 original, IR::U128 shifted) { +IR::U128 PerformRoundingCorrection(TranslatorVisitor& v, size_t esize, u64 round_value, IR::U128 original, IR::U128 shifted) { const auto round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value)); const auto round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(original, round_const), round_const); return v.ir.VectorSub(esize, shifted, round_correction); @@ -61,7 +58,7 @@ std::pair ElementSizeAndShiftAmount(bool right_shift, bool L, si } } -bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, Accumulating accumulate, RoundingATRS RoundingATRS) { +bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, Accumulating accumulate, Rounding rounding) { if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return v.DecodeError(); } @@ -78,9 +75,9 @@ bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bo auto result = U ? v.ir.VectorLogicalShiftRight(esize, reg_m, static_cast(shift_amount)) : v.ir.VectorArithmeticShiftRight(esize, reg_m, static_cast(shift_amount)); - if (RoundingATRS == RoundingATRS::Round) { + if (rounding == Rounding::Round) { const u64 round_value = 1ULL << (shift_amount - 1); - result = PerformRoundingATRSCorrection(v, esize, round_value, reg_m, result); + result = PerformRoundingCorrection(v, esize, round_value, reg_m, result); } if (accumulate == Accumulating::Accumulate) { @@ -92,7 +89,7 @@ bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bo return true; } -bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm, RoundingATRS RoundingATRS, Narrowing narrowing, Signedness signedness) { +bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm, Rounding rounding, Narrowing narrowing, Signedness signedness) { if (mcl::bit::get_bits<3, 5>(imm6) == 0) { return v.DecodeError(); } @@ -116,9 +113,9 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b return v.ir.VectorLogicalShiftRight(source_esize, reg_m, shift_amount); }(); - if (RoundingATRS == RoundingATRS::Round) { + if (rounding == Rounding::Round) { const u64 round_value = 1ULL << (shift_amount - 1); - wide_result = PerformRoundingATRSCorrection(v, source_esize, round_value, reg_m, wide_result); + wide_result = PerformRoundingCorrection(v, source_esize, round_value, reg_m, wide_result); } const auto result = [&] { @@ -144,22 +141,22 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b bool TranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, - Accumulating::None, RoundingATRS::None); + Accumulating::None, Rounding::None); } bool TranslatorVisitor::asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, - Accumulating::Accumulate, RoundingATRS::None); + Accumulating::Accumulate, Rounding::None); } bool TranslatorVisitor::asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, - Accumulating::None, RoundingATRS::Round); + Accumulating::None, Rounding::Round); } bool TranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, - Accumulating::Accumulate, RoundingATRS::Round); + Accumulating::Accumulate, Rounding::Round); } bool TranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { @@ -274,32 +271,32 @@ bool TranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool bool TranslatorVisitor::asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::None, Narrowing::Truncation, Signedness::Unsigned); + Rounding::None, Narrowing::Truncation, Signedness::Unsigned); } bool TranslatorVisitor::asimd_VRSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::Round, Narrowing::Truncation, Signedness::Unsigned); + Rounding::Round, Narrowing::Truncation, Signedness::Unsigned); } bool TranslatorVisitor::asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); + Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); } bool TranslatorVisitor::asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::None, Narrowing::SaturateToUnsigned, Signedness::Signed); + Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed); } bool TranslatorVisitor::asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::None, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); + Rounding::None, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); } bool TranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, - RoundingATRS::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); + Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); } bool TranslatorVisitor::asimd_VSHLL(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/extension.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/extension.cpp index 518f8b944e..3ee6a670f0 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/extension.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/extension.cpp @@ -4,10 +4,14 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) { + const u8 rotate_by = static_cast(static_cast(rotate) * 8); + return ir.RotateRight(ir.GetRegister(m), ir.Imm8(rotate_by), ir.Imm1(0)).result; +} + // SXTAB , , {, } bool TranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { if (d == Reg::PC || m == Reg::PC) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/saturated.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/saturated.cpp index 2371e54ae7..41db115044 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/saturated.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/saturated.cpp @@ -4,10 +4,17 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) { + return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result); +} + +static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) { + return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result); +} + // Saturation instructions // SSAT , #, {, } diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp index 874edd4e16..1a6767dbee 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp @@ -1,18 +1,21 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) { + return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result); +} + +static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) { + return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result); +} using SaturationFunction = IR::ResultAndOverflow (IREmitter::*)(const IR::U32&, size_t); diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp index 1498ac6c7b..1dda532d92 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp @@ -4,10 +4,13 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { namespace { +IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) { + const u8 rotate_by = static_cast(static_cast(rotate) * 8); + return ir.RotateRight(ir.GetRegister(m), ir.Imm8(rotate_by), ir.Imm1(0)).result; +} using ShiftFunction = IR::ResultAndCarry (IREmitter::*)(const IR::U32&, const IR::U8&, const IR::U1&); diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp index d309d42d66..42b2ebf4aa 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp @@ -25,9 +25,9 @@ static bool PLIHandler(TranslatorVisitor& v) { return v.RaiseException(Exception::PreloadInstruction); } -using ExtensionFunctionU8 = IR::U32 (IREmitter::*)(const IR::U8&); +using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U8&); -static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunctionU8 ext_fn) { +static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const u32 base = v.ir.AlignPC(4); const u32 address = U ? (base + imm32) : (base - imm32); @@ -37,7 +37,7 @@ static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, return true; } -static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunctionU8 ext_fn) { +static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunction ext_fn) { if (m == Reg::PC) { return v.UnpredictableInstruction(); } @@ -52,7 +52,7 @@ static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Re return true; } -static bool LoadByteImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunctionU8 ext_fn) { +static bool LoadByteImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const IR::U32 reg_n = v.ir.GetRegister(n); const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32)) diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp index d8a043e553..5b9f1639af 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp @@ -4,11 +4,12 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { -static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunctionU16 ext_fn) { +using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U16&); + +static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunction ext_fn) { const auto imm32 = imm12.ZeroExtend(); const auto base = v.ir.AlignPC(4); const auto address = U ? (base + imm32) : (base - imm32); @@ -18,7 +19,7 @@ static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, return true; } -static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunctionU16 ext_fn) { +static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunction ext_fn) { if (m == Reg::PC) { return v.UnpredictableInstruction(); } @@ -33,7 +34,7 @@ static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Re return true; } -static bool LoadHalfImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunctionU16 ext_fn) { +static bool LoadHalfImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const IR::U32 reg_n = v.ir.GetRegister(n); const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32)) diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp index eb574d773c..17d4285c23 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp @@ -6,9 +6,11 @@ #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static bool ITBlockCheck(const A32::IREmitter& ir) { + return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock(); +} static bool TableBranch(TranslatorVisitor& v, Reg n, Reg m, bool half) { if (m == Reg::PC) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp index d446fbf3dd..2bc782b973 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp @@ -6,9 +6,11 @@ #include #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static bool ITBlockCheck(const A32::IREmitter& ir) { + return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock(); +} static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32& start_address, const IR::U32& writeback_address) { auto address = start_address; diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp index b7556a8caa..b92e27fc66 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp @@ -4,9 +4,11 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static bool ITBlockCheck(const A32::IREmitter& ir) { + return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock(); +} bool TranslatorVisitor::thumb32_LDR_lit(bool U, Reg t, Imm<12> imm12) { if (t == Reg::PC && ITBlockCheck(ir)) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp index 64d57e917d..654940967d 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp @@ -4,9 +4,15 @@ */ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/frontend/A32/translate/impl/common.h" namespace Dynarmic::A32 { +static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) { + return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result); +} + +static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) { + return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result); +} bool TranslatorVisitor::thumb32_SADD8(Reg n, Reg d, Reg m) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp index 05316f8992..24b5797de8 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp @@ -1,12 +1,9 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" +#include #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp b/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp index 5bb516ccfd..d61d8ccbff 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.cpp index 68f536c8d5..3f5a70bdc0 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.cpp @@ -5,7 +5,261 @@ #include "dynarmic/frontend/A64/a64_ir_emitter.h" +#include + +#include "dynarmic/ir/opcodes.h" + namespace Dynarmic::A64 { +using Opcode = IR::Opcode; + +u64 IREmitter::PC() const { + return current_location->PC(); +} + +u64 IREmitter::AlignPC(size_t alignment) const { + const u64 pc = PC(); + return static_cast(pc - pc % alignment); +} + +void IREmitter::SetCheckBit(const IR::U1& value) { + Inst(Opcode::A64SetCheckBit, value); +} + +IR::U1 IREmitter::GetCFlag() { + return Inst(Opcode::A64GetCFlag); +} + +IR::U32 IREmitter::GetNZCVRaw() { + return Inst(Opcode::A64GetNZCVRaw); +} + +void IREmitter::SetNZCVRaw(IR::U32 value) { + Inst(Opcode::A64SetNZCVRaw, value); +} + +void IREmitter::SetNZCV(const IR::NZCV& nzcv) { + Inst(Opcode::A64SetNZCV, nzcv); +} + +void IREmitter::CallSupervisor(u32 imm) { + Inst(Opcode::A64CallSupervisor, Imm32(imm)); +} + +void IREmitter::ExceptionRaised(Exception exception) { + Inst(Opcode::A64ExceptionRaised, Imm64(PC()), Imm64(static_cast(exception))); +} + +void IREmitter::DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value) { + Inst(Opcode::A64DataCacheOperationRaised, ImmCurrentLocationDescriptor(), Imm64(static_cast(op)), value); +} + +void IREmitter::InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value) { + Inst(Opcode::A64InstructionCacheOperationRaised, Imm64(static_cast(op)), value); +} + +void IREmitter::DataSynchronizationBarrier() { + Inst(Opcode::A64DataSynchronizationBarrier); +} + +void IREmitter::DataMemoryBarrier() { + Inst(Opcode::A64DataMemoryBarrier); +} + +void IREmitter::InstructionSynchronizationBarrier() { + Inst(Opcode::A64InstructionSynchronizationBarrier); +} + +IR::U32 IREmitter::GetCNTFRQ() { + return Inst(Opcode::A64GetCNTFRQ); +} + +IR::U64 IREmitter::GetCNTPCT() { + return Inst(Opcode::A64GetCNTPCT); +} + +IR::U32 IREmitter::GetCTR() { + return Inst(Opcode::A64GetCTR); +} + +IR::U32 IREmitter::GetDCZID() { + return Inst(Opcode::A64GetDCZID); +} + +IR::U64 IREmitter::GetTPIDR() { + return Inst(Opcode::A64GetTPIDR); +} + +void IREmitter::SetTPIDR(const IR::U64& value) { + Inst(Opcode::A64SetTPIDR, value); +} + +IR::U64 IREmitter::GetTPIDRRO() { + return Inst(Opcode::A64GetTPIDRRO); +} + +void IREmitter::ClearExclusive() { + Inst(Opcode::A64ClearExclusive); +} + +IR::U8 IREmitter::ReadMemory8(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ReadMemory8, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U16 IREmitter::ReadMemory16(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ReadMemory16, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ReadMemory32(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ReadMemory32, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U64 IREmitter::ReadMemory64(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ReadMemory64, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U128 IREmitter::ReadMemory128(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ReadMemory128, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U8 IREmitter::ExclusiveReadMemory8(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveReadMemory8, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U16 IREmitter::ExclusiveReadMemory16(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveReadMemory16, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveReadMemory32(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveReadMemory32, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U64 IREmitter::ExclusiveReadMemory64(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveReadMemory64, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +IR::U128 IREmitter::ExclusiveReadMemory128(const IR::U64& vaddr, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveReadMemory128, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); +} + +void IREmitter::WriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type) { + Inst(Opcode::A64WriteMemory8, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +void IREmitter::WriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type) { + Inst(Opcode::A64WriteMemory16, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +void IREmitter::WriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type) { + Inst(Opcode::A64WriteMemory32, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +void IREmitter::WriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type) { + Inst(Opcode::A64WriteMemory64, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +void IREmitter::WriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type) { + Inst(Opcode::A64WriteMemory128, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveWriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveWriteMemory8, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveWriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveWriteMemory16, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveWriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveWriteMemory32, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveWriteMemory64, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::ExclusiveWriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type) { + return Inst(Opcode::A64ExclusiveWriteMemory128, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); +} + +IR::U32 IREmitter::GetW(Reg reg) { + if (reg == Reg::ZR) + return Imm32(0); + return Inst(Opcode::A64GetW, IR::Value(reg)); +} + +IR::U64 IREmitter::GetX(Reg reg) { + if (reg == Reg::ZR) + return Imm64(0); + return Inst(Opcode::A64GetX, IR::Value(reg)); +} + +IR::U128 IREmitter::GetS(Vec vec) { + return Inst(Opcode::A64GetS, IR::Value(vec)); +} + +IR::U128 IREmitter::GetD(Vec vec) { + return Inst(Opcode::A64GetD, IR::Value(vec)); +} + +IR::U128 IREmitter::GetQ(Vec vec) { + return Inst(Opcode::A64GetQ, IR::Value(vec)); +} + +IR::U64 IREmitter::GetSP() { + return Inst(Opcode::A64GetSP); +} + +IR::U32 IREmitter::GetFPCR() { + return Inst(Opcode::A64GetFPCR); +} + +IR::U32 IREmitter::GetFPSR() { + return Inst(Opcode::A64GetFPSR); +} + +void IREmitter::SetW(const Reg reg, const IR::U32& value) { + if (reg == Reg::ZR) + return; + Inst(Opcode::A64SetW, IR::Value(reg), value); +} + +void IREmitter::SetX(const Reg reg, const IR::U64& value) { + if (reg == Reg::ZR) + return; + Inst(Opcode::A64SetX, IR::Value(reg), value); +} + +void IREmitter::SetS(const Vec vec, const IR::U128& value) { + Inst(Opcode::A64SetS, IR::Value(vec), value); +} + +void IREmitter::SetD(const Vec vec, const IR::U128& value) { + Inst(Opcode::A64SetD, IR::Value(vec), value); +} + +void IREmitter::SetQ(const Vec vec, const IR::U128& value) { + Inst(Opcode::A64SetQ, IR::Value(vec), value); +} + +void IREmitter::SetSP(const IR::U64& value) { + Inst(Opcode::A64SetSP, value); +} + +void IREmitter::SetFPCR(const IR::U32& value) { + Inst(Opcode::A64SetFPCR, value); +} + +void IREmitter::SetFPSR(const IR::U32& value) { + Inst(Opcode::A64SetFPSR, value); +} + +void IREmitter::SetPC(const IR::U64& value) { + Inst(Opcode::A64SetPC, value); +} + +IR::U64 IREmitter::ImmCurrentLocationDescriptor() { + return Imm64(IR::LocationDescriptor{*current_location}.Value()); +} } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h b/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h index 18f32cdcc9..7fc8bea7c4 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h +++ b/externals/dynarmic/src/dynarmic/frontend/A64/a64_ir_emitter.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,15 +7,13 @@ #include -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/assert.h" +#include #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/interface/A64/config.h" #include "dynarmic/ir/ir_emitter.h" #include "dynarmic/ir/value.h" -#include "dynarmic/ir/opcodes.h" namespace Dynarmic::A64 { @@ -29,262 +24,79 @@ namespace Dynarmic::A64 { */ class IREmitter : public IR::IREmitter { public: - explicit IREmitter(IR::Block& block) : IR::IREmitter(block) {} - explicit IREmitter(IR::Block& block, LocationDescriptor descriptor) : IR::IREmitter(block), current_location(descriptor) {} + explicit IREmitter(IR::Block& block) + : IR::IREmitter(block) {} + explicit IREmitter(IR::Block& block, LocationDescriptor descriptor) + : IR::IREmitter(block), current_location(descriptor) {} std::optional current_location; - using Opcode = IR::Opcode; + u64 PC() const; + u64 AlignPC(size_t alignment) const; - u64 PC() const noexcept { - return current_location->PC(); - } + void SetCheckBit(const IR::U1& value); + IR::U1 GetCFlag(); + IR::U32 GetNZCVRaw(); + void SetNZCVRaw(IR::U32 value); + void SetNZCV(const IR::NZCV& nzcv); - u64 AlignPC(size_t alignment) const noexcept { - const u64 pc = PC(); - return static_cast(pc - pc % alignment); - } + void CallSupervisor(u32 imm); + void ExceptionRaised(Exception exception); + void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value); + void InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value); + void DataSynchronizationBarrier(); + void DataMemoryBarrier(); + void InstructionSynchronizationBarrier(); + IR::U32 GetCNTFRQ(); + IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this. + IR::U32 GetCTR(); + IR::U32 GetDCZID(); + IR::U64 GetTPIDR(); + IR::U64 GetTPIDRRO(); + void SetTPIDR(const IR::U64& value); - void SetCheckBit(const IR::U1& value) noexcept { - Inst(Opcode::A64SetCheckBit, value); - } + void ClearExclusive(); + IR::U8 ReadMemory8(const IR::U64& vaddr, IR::AccType acc_type); + IR::U16 ReadMemory16(const IR::U64& vaddr, IR::AccType acc_type); + IR::U32 ReadMemory32(const IR::U64& vaddr, IR::AccType acc_type); + IR::U64 ReadMemory64(const IR::U64& vaddr, IR::AccType acc_type); + IR::U128 ReadMemory128(const IR::U64& vaddr, IR::AccType acc_type); + IR::U8 ExclusiveReadMemory8(const IR::U64& vaddr, IR::AccType acc_type); + IR::U16 ExclusiveReadMemory16(const IR::U64& vaddr, IR::AccType acc_type); + IR::U32 ExclusiveReadMemory32(const IR::U64& vaddr, IR::AccType acc_type); + IR::U64 ExclusiveReadMemory64(const IR::U64& vaddr, IR::AccType acc_type); + IR::U128 ExclusiveReadMemory128(const IR::U64& vaddr, IR::AccType acc_type); + void WriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type); + void WriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type); + void WriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type); + void WriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type); + void WriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type); + IR::U32 ExclusiveWriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type); + IR::U32 ExclusiveWriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type); + IR::U32 ExclusiveWriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type); + IR::U32 ExclusiveWriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type); + IR::U32 ExclusiveWriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type); - IR::U1 GetCFlag() noexcept { - return Inst(Opcode::A64GetCFlag); - } - - IR::U32 GetNZCVRaw() noexcept { - return Inst(Opcode::A64GetNZCVRaw); - } - - void SetNZCVRaw(IR::U32 value) noexcept { - Inst(Opcode::A64SetNZCVRaw, value); - } - - void SetNZCV(const IR::NZCV& nzcv) noexcept { - Inst(Opcode::A64SetNZCV, nzcv); - } - - void CallSupervisor(u32 imm) noexcept { - Inst(Opcode::A64CallSupervisor, Imm32(imm)); - } - - void ExceptionRaised(Exception exception) noexcept { - Inst(Opcode::A64ExceptionRaised, Imm64(PC()), Imm64(static_cast(exception))); - } - - void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value) noexcept { - Inst(Opcode::A64DataCacheOperationRaised, ImmCurrentLocationDescriptor(), Imm64(static_cast(op)), value); - } - - void InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value) noexcept { - Inst(Opcode::A64InstructionCacheOperationRaised, Imm64(static_cast(op)), value); - } - - void DataSynchronizationBarrier() noexcept { - Inst(Opcode::A64DataSynchronizationBarrier); - } - - void DataMemoryBarrier() noexcept { - Inst(Opcode::A64DataMemoryBarrier); - } - - void InstructionSynchronizationBarrier() noexcept { - Inst(Opcode::A64InstructionSynchronizationBarrier); - } - - IR::U32 GetCNTFRQ() noexcept { - return Inst(Opcode::A64GetCNTFRQ); - } - - IR::U64 GetCNTPCT() noexcept { - return Inst(Opcode::A64GetCNTPCT); - } - - IR::U32 GetCTR() noexcept { - return Inst(Opcode::A64GetCTR); - } - - IR::U32 GetDCZID() noexcept { - return Inst(Opcode::A64GetDCZID); - } - - IR::U64 GetTPIDR() noexcept { - return Inst(Opcode::A64GetTPIDR); - } - - void SetTPIDR(const IR::U64& value) noexcept { - Inst(Opcode::A64SetTPIDR, value); - } - - IR::U64 GetTPIDRRO() noexcept { - return Inst(Opcode::A64GetTPIDRRO); - } - - void ClearExclusive() noexcept { - Inst(Opcode::A64ClearExclusive); - } - - IR::U8 ReadMemory8(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ReadMemory8, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U16 ReadMemory16(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ReadMemory16, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U32 ReadMemory32(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ReadMemory32, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U64 ReadMemory64(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ReadMemory64, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U128 ReadMemory128(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ReadMemory128, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U8 ExclusiveReadMemory8(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveReadMemory8, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U16 ExclusiveReadMemory16(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveReadMemory16, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U32 ExclusiveReadMemory32(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveReadMemory32, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U64 ExclusiveReadMemory64(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveReadMemory64, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - IR::U128 ExclusiveReadMemory128(const IR::U64& vaddr, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveReadMemory128, ImmCurrentLocationDescriptor(), vaddr, IR::Value{acc_type}); - } - - void WriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type) noexcept { - Inst(Opcode::A64WriteMemory8, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - void WriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type) noexcept { - Inst(Opcode::A64WriteMemory16, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - void WriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type) noexcept { - Inst(Opcode::A64WriteMemory32, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - void WriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type) noexcept { - Inst(Opcode::A64WriteMemory64, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - void WriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type) noexcept { - Inst(Opcode::A64WriteMemory128, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 ExclusiveWriteMemory8(const IR::U64& vaddr, const IR::U8& value, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveWriteMemory8, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 ExclusiveWriteMemory16(const IR::U64& vaddr, const IR::U16& value, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveWriteMemory16, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 ExclusiveWriteMemory32(const IR::U64& vaddr, const IR::U32& value, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveWriteMemory32, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 ExclusiveWriteMemory64(const IR::U64& vaddr, const IR::U64& value, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveWriteMemory64, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 ExclusiveWriteMemory128(const IR::U64& vaddr, const IR::U128& value, IR::AccType acc_type) noexcept { - return Inst(Opcode::A64ExclusiveWriteMemory128, ImmCurrentLocationDescriptor(), vaddr, value, IR::Value{acc_type}); - } - - IR::U32 GetW(Reg reg) noexcept { - if (reg == Reg::ZR) - return Imm32(0); - return Inst(Opcode::A64GetW, IR::Value(reg)); - } - - IR::U64 GetX(Reg reg) noexcept { - if (reg == Reg::ZR) - return Imm64(0); - return Inst(Opcode::A64GetX, IR::Value(reg)); - } - - IR::U128 GetS(Vec vec) noexcept { - return Inst(Opcode::A64GetS, IR::Value(vec)); - } - - IR::U128 GetD(Vec vec) noexcept { - return Inst(Opcode::A64GetD, IR::Value(vec)); - } - - IR::U128 GetQ(Vec vec) noexcept { - return Inst(Opcode::A64GetQ, IR::Value(vec)); - } - - IR::U64 GetSP() noexcept { - return Inst(Opcode::A64GetSP); - } - - IR::U32 GetFPCR() noexcept { - return Inst(Opcode::A64GetFPCR); - } - - IR::U32 GetFPSR() noexcept { - return Inst(Opcode::A64GetFPSR); - } - - void SetW(const Reg reg, const IR::U32& value) noexcept { - if (reg == Reg::ZR) - return; - Inst(Opcode::A64SetW, IR::Value(reg), value); - } - - void SetX(const Reg reg, const IR::U64& value) noexcept { - if (reg == Reg::ZR) - return; - Inst(Opcode::A64SetX, IR::Value(reg), value); - } - - void SetS(const Vec vec, const IR::U128& value) noexcept { - Inst(Opcode::A64SetS, IR::Value(vec), value); - } - - void SetD(const Vec vec, const IR::U128& value) noexcept { - Inst(Opcode::A64SetD, IR::Value(vec), value); - } - - void SetQ(const Vec vec, const IR::U128& value) noexcept { - Inst(Opcode::A64SetQ, IR::Value(vec), value); - } - - void SetSP(const IR::U64& value) noexcept { - Inst(Opcode::A64SetSP, value); - } - - void SetFPCR(const IR::U32& value) noexcept { - Inst(Opcode::A64SetFPCR, value); - } - - void SetFPSR(const IR::U32& value) noexcept { - Inst(Opcode::A64SetFPSR, value); - } - - void SetPC(const IR::U64& value) noexcept { - Inst(Opcode::A64SetPC, value); - } + IR::U32 GetW(Reg source_reg); + IR::U64 GetX(Reg source_reg); + IR::U128 GetS(Vec source_vec); + IR::U128 GetD(Vec source_vec); + IR::U128 GetQ(Vec source_vec); + IR::U64 GetSP(); + IR::U32 GetFPCR(); + IR::U32 GetFPSR(); + void SetW(Reg dest_reg, const IR::U32& value); + void SetX(Reg dest_reg, const IR::U64& value); + void SetS(Vec dest_vec, const IR::U128& value); + void SetD(Vec dest_vec, const IR::U128& value); + void SetQ(Vec dest_vec, const IR::U128& value); + void SetSP(const IR::U64& value); + void SetFPCR(const IR::U32& value); + void SetFPSR(const IR::U32& value); + void SetPC(const IR::U64& value); private: - IR::U64 ImmCurrentLocationDescriptor() noexcept { - return Imm64(IR::LocationDescriptor{*current_location}.Value()); - } + IR::U64 ImmCurrentLocationDescriptor(); }; } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h b/externals/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h index 4bfc5f890e..122bebbcb7 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h +++ b/externals/dynarmic/src/dynarmic/frontend/A64/a64_location_descriptor.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,7 +11,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/a64_types.h b/externals/dynarmic/src/dynarmic/frontend/A64/a64_types.h index 8d0f0abe80..6bc7a24536 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/a64_types.h +++ b/externals/dynarmic/src/dynarmic/frontend/A64/a64_types.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,8 +8,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/ir/cond.h" diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h b/externals/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h index c651dd7cde..f264893502 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h +++ b/externals/dynarmic/src/dynarmic/frontend/A64/decoder/a64.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -16,7 +13,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" @@ -36,26 +33,27 @@ inline size_t ToFastLookupIndex(u32 instruction) { } // namespace detail template -constexpr DecodeTable GetDecodeTable() { +DecodeTable GetDecodeTable() { std::vector> list = { #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)), #include "./a64.inc" #undef INST }; - // If a matcher has more bits in its mask it is more specific, so it should come first. std::stable_sort(list.begin(), list.end(), [](const auto& matcher1, const auto& matcher2) { // If a matcher has more bits in its mask it is more specific, so it should come first. return mcl::bit::count_ones(matcher1.GetMask()) > mcl::bit::count_ones(matcher2.GetMask()); }); // Exceptions to the above rule of thumb. + const std::set comes_first{ + "MOVI, MVNI, ORR, BIC (vector, immediate)", + "FMOV (vector, immediate)", + "Unallocated SIMD modified immediate", + }; + std::stable_partition(list.begin(), list.end(), [&](const auto& matcher) { - return std::set{ - "MOVI, MVNI, ORR, BIC (vector, immediate)", - "FMOV (vector, immediate)", - "Unallocated SIMD modified immediate", - }.count(matcher.GetName()) > 0; + return comes_first.count(matcher.GetName()) > 0; }); DecodeTable table{}; @@ -77,6 +75,7 @@ std::optional>> Decode(u32 instruction) const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; + const auto& subtable = table[detail::ToFastLookupIndex(instruction)]; auto iter = std::find_if(subtable.begin(), subtable.end(), matches_instruction); return iter != subtable.end() ? std::optional>>(*iter) : std::nullopt; diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp index 352c2e6ae2..05996aeb64 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp @@ -67,64 +67,3 @@ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, } } // namespace Dynarmic::A64 - -// ls -l | awk '{print "#include \"dynarmic/frontend/A64/translate/impl/" $9 "\""}' -#include "dynarmic/frontend/A64/translate/impl/a64_branch.cpp" -#include "dynarmic/frontend/A64/translate/impl/a64_exception_generating.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_addsub.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_bitfield.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_conditional_compare.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_conditional_select.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_crc32.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_logical.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_multiply.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_pcrel.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/data_processing_shift.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_compare.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_conditional_compare.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_conditional_select.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/impl.cpp" -#include "dynarmic/frontend/A64/translate/impl/impl.h" -#include "dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_load_literal.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_no_allocate_pair.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_register_unprivileged.cpp" -#include "dynarmic/frontend/A64/translate/impl/load_store_single_structure.cpp" -#include "dynarmic/frontend/A64/translate/impl/move_wide.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_aes.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_copy.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_crypto_four_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_crypto_three_register.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_extract.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_permute.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_sha512.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_sha.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_table_lookup.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_three_different.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_three_same.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp" -#include "dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp" -#include "dynarmic/frontend/A64/translate/impl/sys_dc.cpp" -#include "dynarmic/frontend/A64/translate/impl/sys_ic.cpp" -#include "dynarmic/frontend/A64/translate/impl/system.cpp" -#include "dynarmic/frontend/A64/translate/impl/system_flag_format.cpp" -#include "dynarmic/frontend/A64/translate/impl/system_flag_manipulation.cpp" diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h b/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h index be55fb3970..2f62ac6e50 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp index e3b8d7502c..63615b0f9a 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp @@ -7,14 +7,14 @@ namespace Dynarmic::A64 { namespace { -enum class MinMaxOperationSSPW { +enum class MinMaxOperation { Max, MaxNumeric, Min, MinNumeric, }; -bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOperationSSPW operation) { +bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOperation operation) { const size_t esize = sz ? 64 : 32; const IR::U128 operand = v.V(128, Vn); @@ -22,13 +22,13 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera const IR::U32U64 element2 = v.ir.VectorGetElement(esize, operand, 1); const IR::U32U64 result = [&] { switch (operation) { - case MinMaxOperationSSPW::Max: + case MinMaxOperation::Max: return v.ir.FPMax(element1, element2); - case MinMaxOperationSSPW::MaxNumeric: + case MinMaxOperation::MaxNumeric: return v.ir.FPMaxNumeric(element1, element2); - case MinMaxOperationSSPW::Min: + case MinMaxOperation::Min: return v.ir.FPMin(element1, element2); - case MinMaxOperationSSPW::MinNumeric: + case MinMaxOperation::MinNumeric: return v.ir.FPMinNumeric(element1, element2); default: UNREACHABLE(); @@ -63,18 +63,18 @@ bool TranslatorVisitor::FADDP_pair_2(bool size, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd) { - return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperationSSPW::MaxNumeric); + return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::MaxNumeric); } bool TranslatorVisitor::FMAXP_pair_2(bool sz, Vec Vn, Vec Vd) { - return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperationSSPW::Max); + return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Max); } bool TranslatorVisitor::FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) { - return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperationSSPW::MinNumeric); + return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::MinNumeric); } bool TranslatorVisitor::FMINP_pair_2(bool sz, Vec Vn, Vec Vd) { - return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperationSSPW::Min); + return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Min); } } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp index 5d60cb31c3..a0570edc7e 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp @@ -27,7 +27,7 @@ enum class ShiftExtraBehavior { Accumulate, }; -enum class SignednessSSSBI { +enum class Signedness { Signed, Unsigned, }; @@ -63,7 +63,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, return true; } -bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, SignednessSSSBI SignednessSSSBI) { +bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, Signedness signedness) { if (!immh.Bit<3>()) { return v.ReservedValue(); } @@ -73,7 +73,7 @@ bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, const IR::U64 operand = v.V_scalar(esize, Vn); IR::U64 result = [&]() -> IR::U64 { - if (SignednessSSSBI == SignednessSSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.ArithmeticShiftRight(operand, v.ir.Imm8(shift_amount)); } return v.ir.LogicalShiftRight(operand, v.ir.Imm8(shift_amount)); @@ -88,7 +88,7 @@ bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, return true; } -bool RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, SignednessSSSBI SignednessSSSBI) { +bool RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, Signedness signedness) { if (!immh.Bit<3>()) { return v.ReservedValue(); } @@ -100,7 +100,7 @@ bool RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, const IR::U64 round_bit = v.ir.LogicalShiftRight(v.ir.LogicalShiftLeft(operand, v.ir.Imm8(64 - shift_amount)), v.ir.Imm8(63)); const IR::U64 result = [&] { const IR::U64 shifted = [&]() -> IR::U64 { - if (SignednessSSSBI == SignednessSSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.ArithmeticShiftRight(operand, v.ir.Imm8(shift_amount)); } return v.ir.LogicalShiftRight(operand, v.ir.Imm8(shift_amount)); @@ -163,7 +163,7 @@ bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec return true; } -bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Narrowing narrowing, SignednessSSSBI SignednessSSSBI) { +bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Narrowing narrowing, Signedness signedness) { if (immh == 0b0000) { return v.ReservedValue(); } @@ -179,7 +179,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, const IR::U128 operand = v.ir.ZeroExtendToQuad(v.ir.VectorGetElement(source_esize, v.V(128, Vn), 0)); IR::U128 wide_result = [&] { - if (SignednessSSSBI == SignednessSSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.VectorArithmeticShiftRight(source_esize, operand, shift_amount); } return v.ir.VectorLogicalShiftRight(source_esize, operand, shift_amount); @@ -190,12 +190,12 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, case Narrowing::Truncation: return v.ir.VectorNarrow(source_esize, wide_result); case Narrowing::SaturateToUnsigned: - if (SignednessSSSBI == SignednessSSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.VectorSignedSaturatedNarrowToUnsigned(source_esize, wide_result); } return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result); case Narrowing::SaturateToSigned: - ASSERT(SignednessSSSBI == SignednessSSSBI::Signed); + ASSERT(signedness == Signedness::Signed); return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result); } UNREACHABLE(); @@ -206,7 +206,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, return true; } -bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, SignednessSSSBI sign, FloatConversionDirection direction, FP::RoundingMode rounding_mode) { +bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Signedness sign, FloatConversionDirection direction, FP::RoundingMode rounding_mode) { const u32 immh_value = immh.ZeroExtend(); if ((immh_value & 0b1110) == 0b0000) { @@ -227,23 +227,23 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve switch (direction) { case FloatConversionDirection::FloatToFixed: if (esize == 64) { - return sign == SignednessSSSBI::Signed + return sign == Signedness::Signed ? v.ir.FPToFixedS64(operand, fbits, rounding_mode) : v.ir.FPToFixedU64(operand, fbits, rounding_mode); } - return sign == SignednessSSSBI::Signed + return sign == Signedness::Signed ? v.ir.FPToFixedS32(operand, fbits, rounding_mode) : v.ir.FPToFixedU32(operand, fbits, rounding_mode); case FloatConversionDirection::FixedToFloat: if (esize == 64) { - return sign == SignednessSSSBI::Signed + return sign == Signedness::Signed ? v.ir.FPSignedFixedToDouble(operand, fbits, rounding_mode) : v.ir.FPUnsignedFixedToDouble(operand, fbits, rounding_mode); } - return sign == SignednessSSSBI::Signed + return sign == Signedness::Signed ? v.ir.FPSignedFixedToSingle(operand, fbits, rounding_mode) : v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode); } @@ -257,19 +257,19 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve } // Anonymous namespace bool TranslatorVisitor::FCVTZS_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, SignednessSSSBI::Signed, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); + return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, Signedness::Signed, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); } bool TranslatorVisitor::FCVTZU_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, SignednessSSSBI::Unsigned, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); + return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, Signedness::Unsigned, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); } bool TranslatorVisitor::SCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, SignednessSSSBI::Signed, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); + return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, Signedness::Signed, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); } bool TranslatorVisitor::UCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, SignednessSSSBI::Unsigned, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); + return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, Signedness::Unsigned, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); } bool TranslatorVisitor::SLI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -289,27 +289,27 @@ bool TranslatorVisitor::SQSHLU_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToSigned, SignednessSSSBI::Signed); + return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToSigned, Signedness::Signed); } bool TranslatorVisitor::SQSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToUnsigned, SignednessSSSBI::Signed); + return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToUnsigned, Signedness::Signed); } bool TranslatorVisitor::SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, SignednessSSSBI::Signed); + return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed); } bool TranslatorVisitor::SRSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, SignednessSSSBI::Signed); + return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, SignednessSSSBI::Signed); + return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Signed); } bool TranslatorVisitor::SSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, SignednessSSSBI::Signed); + return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -332,23 +332,23 @@ bool TranslatorVisitor::UQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { } bool TranslatorVisitor::UQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToUnsigned, SignednessSSSBI::Unsigned); + return ShiftRightNarrowing(*this, immh, immb, Vn, Vd, Narrowing::SaturateToUnsigned, Signedness::Unsigned); } bool TranslatorVisitor::URSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, SignednessSSSBI::Unsigned); + return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned); } bool TranslatorVisitor::URSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, SignednessSSSBI::Unsigned); + return RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, SignednessSSSBI::Unsigned); + return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None, Signedness::Unsigned); } bool TranslatorVisitor::USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, SignednessSSSBI::Unsigned); + return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned); } } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp index d551605bda..fb9ae9d141 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp @@ -26,12 +26,12 @@ enum class ComparisonVariant { Zero, }; -enum class SignednessSSTS { +enum class Signedness { Signed, Unsigned, }; -bool RoundingShiftLeft(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, SignednessSSTS sign) { +bool RoundingShiftLeft(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) { if (size != 0b11) { return v.ReservedValue(); } @@ -39,7 +39,7 @@ bool RoundingShiftLeft(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd const IR::U128 operand1 = v.V(64, Vn); const IR::U128 operand2 = v.V(64, Vm); const IR::U128 result = [&] { - if (sign == SignednessSSTS::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorRoundingShiftLeftSigned(64, operand1, operand2); } @@ -369,7 +369,7 @@ bool TranslatorVisitor::SQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingShiftLeft(*this, size, Vm, Vn, Vd, SignednessSSTS::Signed); + return RoundingShiftLeft(*this, size, Vm, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -411,7 +411,7 @@ bool TranslatorVisitor::UQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::URSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingShiftLeft(*this, size, Vm, Vn, Vd, SignednessSSTS::Unsigned); + return RoundingShiftLeft(*this, size, Vm, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index 0fc37f538f..2289f5cbd1 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -7,7 +7,7 @@ namespace Dynarmic::A64 { namespace { -enum class ComparisonTypeSSTRM { +enum class ComparisonType { EQ, GE, GT, @@ -15,12 +15,12 @@ enum class ComparisonTypeSSTRM { LT }; -enum class SignednessSSTRM { +enum class Signedness { Signed, Unsigned }; -bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, ComparisonTypeSSTRM type) { +bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, ComparisonType type) { const size_t esize = sz ? 64 : 32; const size_t datasize = esize; @@ -28,15 +28,15 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C const IR::U128 zero = v.ir.ZeroVector(); const IR::U128 result = [&] { switch (type) { - case ComparisonTypeSSTRM::EQ: + case ComparisonType::EQ: return v.ir.FPVectorEqual(esize, operand, zero); - case ComparisonTypeSSTRM::GE: + case ComparisonType::GE: return v.ir.FPVectorGreaterEqual(esize, operand, zero); - case ComparisonTypeSSTRM::GT: + case ComparisonType::GT: return v.ir.FPVectorGreater(esize, operand, zero); - case ComparisonTypeSSTRM::LE: + case ComparisonType::LE: return v.ir.FPVectorGreaterEqual(esize, zero, operand); - case ComparisonTypeSSTRM::LT: + case ComparisonType::LT: return v.ir.FPVectorGreater(esize, zero, operand); } @@ -47,18 +47,18 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C return true; } -bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, FP::RoundingMode rmode, SignednessSSTRM sign) { +bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, FP::RoundingMode rmode, Signedness sign) { const size_t esize = sz ? 64 : 32; const IR::U32U64 operand = v.V_scalar(esize, Vn); const IR::U32U64 result = [&]() -> IR::U32U64 { if (sz) { - return sign == SignednessSSTRM::Signed + return sign == Signedness::Signed ? v.ir.FPToFixedS64(operand, 0, rmode) : v.ir.FPToFixedU64(operand, 0, rmode); } - return sign == SignednessSSTRM::Signed + return sign == Signedness::Signed ? v.ir.FPToFixedS32(operand, 0, rmode) : v.ir.FPToFixedU32(operand, 0, rmode); }(); @@ -107,55 +107,55 @@ bool TranslatorVisitor::FCMEQ_zero_1(Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCMEQ_zero_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonTypeSSTRM::EQ); + return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::EQ); } bool TranslatorVisitor::FCMGE_zero_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonTypeSSTRM::GE); + return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::GE); } bool TranslatorVisitor::FCMGT_zero_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonTypeSSTRM::GT); + return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::GT); } bool TranslatorVisitor::FCMLE_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonTypeSSTRM::LE); + return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::LE); } bool TranslatorVisitor::FCMLT_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonTypeSSTRM::LT); + return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::LT); } bool TranslatorVisitor::FCVTAS_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, SignednessSSTRM::Signed); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, Signedness::Signed); } bool TranslatorVisitor::FCVTAU_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, SignednessSSTRM::Unsigned); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, Signedness::Unsigned); } bool TranslatorVisitor::FCVTMS_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, SignednessSSTRM::Signed); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, Signedness::Signed); } bool TranslatorVisitor::FCVTMU_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, SignednessSSTRM::Unsigned); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, Signedness::Unsigned); } bool TranslatorVisitor::FCVTNS_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, SignednessSSTRM::Signed); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, Signedness::Signed); } bool TranslatorVisitor::FCVTNU_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, SignednessSSTRM::Unsigned); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, Signedness::Unsigned); } bool TranslatorVisitor::FCVTPS_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, SignednessSSTRM::Signed); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Signed); } bool TranslatorVisitor::FCVTPU_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, SignednessSSTRM::Unsigned); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Unsigned); } bool TranslatorVisitor::FCVTXN_1(bool sz, Vec Vn, Vec Vd) { @@ -171,11 +171,11 @@ bool TranslatorVisitor::FCVTXN_1(bool sz, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, SignednessSSTRM::Signed); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Signed); } bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) { - return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, SignednessSSTRM::Unsigned); + return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned); } bool TranslatorVisitor::FRECPE_1(Vec Vn, Vec Vd) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index 7a5d9847d7..dbbc4ce12c 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -9,7 +9,7 @@ namespace Dynarmic::A64 { namespace { -std::pair CombineScalar(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, Imm<4> Vmlo) { +std::pair Combine(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, Imm<4> Vmlo) { if (size == 0b01) { return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend()}; } @@ -122,7 +122,7 @@ bool TranslatorVisitor::SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm } const size_t esize = 8 << size.ZeroExtend(); - const auto [index, Vm] = CombineScalar(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::UAny operand1 = V_scalar(esize, Vn); const IR::UAny operand2 = ir.VectorGetElement(esize, V(128, Vm), index); @@ -137,7 +137,7 @@ bool TranslatorVisitor::SQRDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> V } const size_t esize = 8 << size.ZeroExtend(); - const auto [index, Vm] = CombineScalar(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0)); const IR::U128 operand2 = V(128, Vm); @@ -154,7 +154,7 @@ bool TranslatorVisitor::SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm } const size_t esize = 8 << size.ZeroExtend(); - const auto [index, Vm] = CombineScalar(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0)); const IR::U128 operand2 = V(128, Vm); diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 559721a22a..41b0952249 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -20,24 +20,24 @@ enum class Accumulating { Accumulate }; -enum class SignednessSSBI { +enum class Signedness { Signed, Unsigned }; -enum class NarrowingSSBI { +enum class Narrowing { Truncation, SaturateToUnsigned, SaturateToSigned, }; -enum class SaturatingShiftLeftTypeSSBI { +enum class SaturatingShiftLeftType { Signed, Unsigned, SignedWithUnsignedSaturation, }; -enum class FloatConversionDirectionSSBI { +enum class FloatConversionDirection { FixedToFloat, FloatToFixed, }; @@ -48,7 +48,7 @@ IR::U128 PerformRoundingCorrection(TranslatorVisitor& v, size_t esize, u64 round return v.ir.VectorSub(esize, shifted, round_correction); } -bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, Accumulating accumulating, SignednessSSBI SignednessSSBI) { +bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, Accumulating accumulating, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -65,7 +65,7 @@ bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, const IR::U128 operand = v.V(datasize, Vn); IR::U128 result = [&] { - if (SignednessSSBI == SignednessSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.VectorArithmeticShiftRight(esize, operand, shift_amount); } return v.ir.VectorLogicalShiftRight(esize, operand, shift_amount); @@ -85,7 +85,7 @@ bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, return true; } -bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, NarrowingSSBI NarrowingSSBI, SignednessSSBI SignednessSSBI) { +bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, Narrowing narrowing, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -103,7 +103,7 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i const IR::U128 operand = v.V(128, Vn); IR::U128 wide_result = [&] { - if (SignednessSSBI == SignednessSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.VectorArithmeticShiftRight(source_esize, operand, shift_amount); } return v.ir.VectorLogicalShiftRight(source_esize, operand, shift_amount); @@ -115,16 +115,16 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i } const IR::U128 result = [&] { - switch (NarrowingSSBI) { - case NarrowingSSBI::Truncation: + switch (narrowing) { + case Narrowing::Truncation: return v.ir.VectorNarrow(source_esize, wide_result); - case NarrowingSSBI::SaturateToUnsigned: - if (SignednessSSBI == SignednessSSBI::Signed) { + case Narrowing::SaturateToUnsigned: + if (signedness == Signedness::Signed) { return v.ir.VectorSignedSaturatedNarrowToUnsigned(source_esize, wide_result); } return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result); - case NarrowingSSBI::SaturateToSigned: - ASSERT(SignednessSSBI == SignednessSSBI::Signed); + case Narrowing::SaturateToSigned: + ASSERT(signedness == Signedness::Signed); return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result); } UNREACHABLE(); @@ -134,7 +134,7 @@ bool ShiftRightNarrowingSSBI(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> i return true; } -bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, SignednessSSBI SignednessSSBI) { +bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -151,7 +151,7 @@ bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec V const IR::U128 operand = v.Vpart(datasize, Vn, part); const IR::U128 expanded_operand = [&] { - if (SignednessSSBI == SignednessSSBI::Signed) { + if (signedness == Signedness::Signed) { return v.ir.VectorSignExtend(esize, operand); } return v.ir.VectorZeroExtend(esize, operand); @@ -162,7 +162,7 @@ bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec V return true; } -bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, SaturatingShiftLeftTypeSSBI type) { +bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, SaturatingShiftLeftType type) { if (!Q && immh.Bit<3>()) { return v.ReservedValue(); } @@ -174,11 +174,11 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, const IR::U128 operand = v.V(datasize, Vn); const IR::U128 shift_vec = v.ir.VectorBroadcast(esize, v.I(esize, shift)); const IR::U128 result = [&] { - if (type == SaturatingShiftLeftTypeSSBI::Signed) { + if (type == SaturatingShiftLeftType::Signed) { return v.ir.VectorSignedSaturatedShiftLeft(esize, operand, shift_vec); } - if (type == SaturatingShiftLeftTypeSSBI::Unsigned) { + if (type == SaturatingShiftLeftType::Unsigned) { return v.ir.VectorUnsignedSaturatedShiftLeft(esize, operand, shift_vec); } @@ -189,7 +189,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, return true; } -bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, SignednessSSBI SignednessSSBI, FloatConversionDirectionSSBI direction, FP::RoundingMode rounding_mode) { +bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Signedness signedness, FloatConversionDirection direction, FP::RoundingMode rounding_mode) { if (immh == 0b0000) { return v.DecodeError(); } @@ -210,12 +210,12 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn const IR::U128 operand = v.V(datasize, Vn); const IR::U128 result = [&] { switch (direction) { - case FloatConversionDirectionSSBI::FixedToFloat: - return SignednessSSBI == SignednessSSBI::Signed + case FloatConversionDirection::FixedToFloat: + return signedness == Signedness::Signed ? v.ir.FPVectorFromSignedFixed(esize, operand, fbits, rounding_mode) : v.ir.FPVectorFromUnsignedFixed(esize, operand, fbits, rounding_mode); - case FloatConversionDirectionSSBI::FloatToFixed: - return SignednessSSBI == SignednessSSBI::Signed + case FloatConversionDirection::FloatToFixed: + return signedness == Signedness::Signed ? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode) : v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode); } @@ -229,19 +229,19 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn } // Anonymous namespace bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, SignednessSSBI::Signed); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, Signedness::Signed); } bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, SignednessSSBI::Signed); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, Signedness::Signed); } bool TranslatorVisitor::SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, SignednessSSBI::Signed); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, SignednessSSBI::Signed); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -264,71 +264,71 @@ bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) } bool TranslatorVisitor::SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::None, NarrowingSSBI::Truncation, SignednessSSBI::Unsigned); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::Truncation, Signedness::Unsigned); } bool TranslatorVisitor::RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::Round, NarrowingSSBI::Truncation, SignednessSSBI::Unsigned); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::Truncation, Signedness::Unsigned); } bool TranslatorVisitor::SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftTypeSSBI::Signed); + return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftType::Signed); } bool TranslatorVisitor::SQSHLU_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftTypeSSBI::SignedWithUnsignedSaturation); + return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftType::SignedWithUnsignedSaturation); } bool TranslatorVisitor::SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::None, NarrowingSSBI::SaturateToSigned, SignednessSSBI::Signed); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToSigned, Signedness::Signed); } bool TranslatorVisitor::SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::Round, NarrowingSSBI::SaturateToSigned, SignednessSSBI::Signed); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToSigned, Signedness::Signed); } bool TranslatorVisitor::SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::None, NarrowingSSBI::SaturateToUnsigned, SignednessSSBI::Signed); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed); } bool TranslatorVisitor::SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::Round, NarrowingSSBI::SaturateToUnsigned, SignednessSSBI::Signed); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); } bool TranslatorVisitor::UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftTypeSSBI::Unsigned); + return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, SaturatingShiftLeftType::Unsigned); } bool TranslatorVisitor::UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::None, NarrowingSSBI::SaturateToUnsigned, SignednessSSBI::Unsigned); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Unsigned); } bool TranslatorVisitor::UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRightNarrowingSSBI(*this, Q, immh, immb, Vn, Vd, Rounding::Round, NarrowingSSBI::SaturateToUnsigned, SignednessSSBI::Unsigned); + return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Unsigned); } bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Signed); + return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, SignednessSSBI::Unsigned); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, Signedness::Unsigned); } bool TranslatorVisitor::URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, SignednessSSBI::Unsigned); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, SignednessSSBI::Unsigned); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, Signedness::Unsigned); } bool TranslatorVisitor::USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, SignednessSSBI::Unsigned); + return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Unsigned); + return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -384,19 +384,19 @@ bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) } bool TranslatorVisitor::SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ConvertFloat(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Signed, FloatConversionDirectionSSBI::FixedToFloat, ir.current_location->FPCR().RMode()); + return ConvertFloat(*this, Q, immh, immb, Vn, Vd, Signedness::Signed, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); } bool TranslatorVisitor::UCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ConvertFloat(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Unsigned, FloatConversionDirectionSSBI::FixedToFloat, ir.current_location->FPCR().RMode()); + return ConvertFloat(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned, FloatConversionDirection::FixedToFloat, ir.current_location->FPCR().RMode()); } bool TranslatorVisitor::FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ConvertFloat(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Signed, FloatConversionDirectionSSBI::FloatToFixed, FP::RoundingMode::TowardsZero); + return ConvertFloat(*this, Q, immh, immb, Vn, Vd, Signedness::Signed, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); } bool TranslatorVisitor::FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - return ConvertFloat(*this, Q, immh, immb, Vn, Vd, SignednessSSBI::Unsigned, FloatConversionDirectionSSBI::FloatToFixed, FP::RoundingMode::TowardsZero); + return ConvertFloat(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); } } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp index 8f460665da..8cc677b652 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp @@ -12,12 +12,12 @@ enum class AbsoluteDifferenceBehavior { Accumulate }; -enum class SignednessSTD { +enum class Signedness { Signed, Unsigned }; -bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsoluteDifferenceBehavior behavior, SignednessSTD sign) { +bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsoluteDifferenceBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -27,7 +27,7 @@ bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, V const IR::U128 operand1 = v.ir.VectorZeroExtend(esize, v.Vpart(datasize, Vn, Q)); const IR::U128 operand2 = v.ir.VectorZeroExtend(esize, v.Vpart(datasize, Vm, Q)); - IR::U128 result = sign == SignednessSTD::Signed ? v.ir.VectorSignedAbsoluteDifference(esize, operand1, operand2) + IR::U128 result = sign == Signedness::Signed ? v.ir.VectorSignedAbsoluteDifference(esize, operand1, operand2) : v.ir.VectorUnsignedAbsoluteDifference(esize, operand1, operand2); if (behavior == AbsoluteDifferenceBehavior::Accumulate) { @@ -45,7 +45,7 @@ enum class MultiplyLongBehavior { Subtract }; -bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MultiplyLongBehavior behavior, SignednessSTD sign) { +bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MultiplyLongBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -59,7 +59,7 @@ bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec const auto reg_n = v.Vpart(datasize, Vn, Q); const auto reg_m = v.Vpart(datasize, Vm, Q); - return sign == SignednessSTD::Signed + return sign == Signedness::Signed ? v.ir.VectorMultiplySignedWiden(esize, reg_n, reg_m) : v.ir.VectorMultiplyUnsignedWiden(esize, reg_n, reg_m); }(); @@ -81,7 +81,7 @@ enum class LongOperationBehavior { Subtraction }; -bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, LongOperationBehavior behavior, SignednessSTD sign) { +bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, LongOperationBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -92,7 +92,7 @@ bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Ve const auto get_operand = [&](Vec vec) { const IR::U128 tmp = v.Vpart(64, vec, part); - if (sign == SignednessSTD::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorSignExtend(esize, tmp); } @@ -118,7 +118,7 @@ enum class WideOperationBehavior { Subtraction }; -bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, WideOperationBehavior behavior, SignednessSTD sign) { +bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, WideOperationBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -130,7 +130,7 @@ bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Ve const IR::U128 operand2 = [&] { const IR::U128 tmp = v.Vpart(64, Vm, part); - if (sign == SignednessSTD::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorSignExtend(esize, tmp); } @@ -166,75 +166,75 @@ bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::Accumulate, SignednessSTD::Signed); + return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::None, SignednessSTD::Signed); + return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::None, Signedness::Signed); } bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Addition, SignednessSTD::Signed); + return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Addition, Signedness::Signed); } bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Addition, SignednessSTD::Signed); + return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Addition, Signedness::Signed); } bool TranslatorVisitor::SMLAL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Accumulate, SignednessSTD::Signed); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SMLSL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Subtract, SignednessSTD::Signed); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Subtract, Signedness::Signed); } bool TranslatorVisitor::SMULL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::None, SignednessSTD::Signed); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::None, Signedness::Signed); } bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Subtraction, SignednessSTD::Signed); + return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Subtraction, Signedness::Signed); } bool TranslatorVisitor::SSUBL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Subtraction, SignednessSTD::Signed); + return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Subtraction, Signedness::Signed); } bool TranslatorVisitor::UADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Addition, SignednessSTD::Unsigned); + return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Addition, Signedness::Unsigned); } bool TranslatorVisitor::UABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::Accumulate, SignednessSTD::Unsigned); + return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::UABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::None, SignednessSTD::Unsigned); + return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::None, Signedness::Unsigned); } bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Addition, SignednessSTD::Unsigned); + return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Addition, Signedness::Unsigned); } bool TranslatorVisitor::UMLAL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Accumulate, SignednessSTD::Unsigned); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::UMLSL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Subtract, SignednessSTD::Unsigned); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::Subtract, Signedness::Unsigned); } bool TranslatorVisitor::UMULL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::None, SignednessSTD::Unsigned); + return MultiplyLong(*this, Q, size, Vm, Vn, Vd, MultiplyLongBehavior::None, Signedness::Unsigned); } bool TranslatorVisitor::USUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Subtraction, SignednessSTD::Unsigned); + return WideOperation(*this, Q, size, Vm, Vn, Vd, WideOperationBehavior::Subtraction, Signedness::Unsigned); } bool TranslatorVisitor::USUBL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Subtraction, SignednessSTD::Unsigned); + return LongOperation(*this, Q, size, Vm, Vn, Vd, LongOperationBehavior::Subtraction, Signedness::Unsigned); } bool TranslatorVisitor::SQDMULL_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp index 1cfc2ced78..5c8bf13aeb 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp @@ -12,12 +12,12 @@ enum class Operation { Subtract, }; -enum class ExtraBehaviorSTS { +enum class ExtraBehavior { None, Round }; -bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, ExtraBehaviorSTS behavior) { +bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, ExtraBehavior behavior) { if (size == 0b11) { return v.ReservedValue(); } @@ -35,7 +35,7 @@ bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, V return v.ir.VectorSub(doubled_esize, operand1, operand2); }(); - if (behavior == ExtraBehaviorSTS::Round) { + if (behavior == ExtraBehavior::Round) { const u64 round_const = 1ULL << (esize - 1); const IR::U128 round_operand = v.ir.VectorBroadcast(doubled_esize, v.I(doubled_esize, round_const)); wide = v.ir.VectorAdd(doubled_esize, wide, round_operand); @@ -48,12 +48,12 @@ bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, V return true; } -enum class AbsDiffExtraBehaviorSTS { +enum class AbsDiffExtraBehavior { None, Accumulate }; -bool SignedAbsoluteDifference(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsDiffExtraBehaviorSTS behavior) { +bool SignedAbsoluteDifference(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsDiffExtraBehavior behavior) { if (size == 0b11) { return v.ReservedValue(); } @@ -66,7 +66,7 @@ bool SignedAbsoluteDifference(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, const IR::U128 result = [&] { const IR::U128 tmp = v.ir.VectorSignedAbsoluteDifference(esize, operand1, operand2); - if (behavior == AbsDiffExtraBehaviorSTS::Accumulate) { + if (behavior == AbsDiffExtraBehavior::Accumulate) { const IR::U128 d = v.V(datasize, Vd); return v.ir.VectorAdd(esize, d, tmp); } @@ -78,12 +78,12 @@ bool SignedAbsoluteDifference(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, return true; } -enum class SignednessSTS { +enum class Signedness { Signed, Unsigned }; -bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, SignednessSTS sign) { +bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -93,14 +93,14 @@ bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec V const IR::U128 operand1 = v.V(datasize, Vm); const IR::U128 operand2 = v.V(datasize, Vn); - const IR::U128 result = sign == SignednessSTS::Signed ? v.ir.VectorRoundingHalvingAddSigned(esize, operand1, operand2) + const IR::U128 result = sign == Signedness::Signed ? v.ir.VectorRoundingHalvingAddSigned(esize, operand1, operand2) : v.ir.VectorRoundingHalvingAddUnsigned(esize, operand1, operand2); v.V(datasize, Vd, result); return true; } -bool RoundingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, SignednessSTS sign) { +bool RoundingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) { if (size == 0b11 && !Q) { return v.ReservedValue(); } @@ -111,7 +111,7 @@ bool RoundingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn const IR::U128 operand1 = v.V(datasize, Vn); const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { - if (sign == SignednessSTS::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorRoundingShiftLeftSigned(esize, operand1, operand2); } @@ -122,7 +122,7 @@ bool RoundingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn return true; } -enum class ComparisonTypeSTS { +enum class ComparisonType { EQ, GE, AbsoluteGE, @@ -130,7 +130,7 @@ enum class ComparisonTypeSTS { AbsoluteGT }; -bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, ComparisonTypeSTS type) { +bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) { if (sz && !Q) { return v.ReservedValue(); } @@ -142,17 +142,17 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { switch (type) { - case ComparisonTypeSTS::EQ: + case ComparisonType::EQ: return v.ir.FPVectorEqual(esize, operand1, operand2); - case ComparisonTypeSTS::GE: + case ComparisonType::GE: return v.ir.FPVectorGreaterEqual(esize, operand1, operand2); - case ComparisonTypeSTS::AbsoluteGE: + case ComparisonType::AbsoluteGE: return v.ir.FPVectorGreaterEqual(esize, v.ir.FPVectorAbs(esize, operand1), v.ir.FPVectorAbs(esize, operand2)); - case ComparisonTypeSTS::GT: + case ComparisonType::GT: return v.ir.FPVectorGreater(esize, operand1, operand2); - case ComparisonTypeSTS::AbsoluteGT: + case ComparisonType::AbsoluteGT: return v.ir.FPVectorGreater(esize, v.ir.FPVectorAbs(esize, operand1), v.ir.FPVectorAbs(esize, operand2)); @@ -165,12 +165,12 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve return true; } -enum class MinMaxOperationSTS { +enum class MinMaxOperation { Min, Max, }; -bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperationSTS operation, SignednessSTS sign) { +bool VectorMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -182,14 +182,14 @@ bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { switch (operation) { - case MinMaxOperationSTS::Max: - if (sign == SignednessSTS::Signed) { + case MinMaxOperation::Max: + if (sign == Signedness::Signed) { return v.ir.VectorMaxSigned(esize, operand1, operand2); } return v.ir.VectorMaxUnsigned(esize, operand1, operand2); - case MinMaxOperationSTS::Min: - if (sign == SignednessSTS::Signed) { + case MinMaxOperation::Min: + if (sign == Signedness::Signed) { return v.ir.VectorMinSigned(esize, operand1, operand2); } return v.ir.VectorMinUnsigned(esize, operand1, operand2); @@ -203,7 +203,7 @@ bool VectorMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, return true; } -bool FPMinMaxOperationSTS(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, MinMaxOperationSTS operation) { +bool FPMinMaxOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation) { if (sz && !Q) { return v.ReservedValue(); } @@ -214,7 +214,7 @@ bool FPMinMaxOperationSTS(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, const IR::U128 operand1 = v.V(datasize, Vn); const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { - if (operation == MinMaxOperationSTS::Min) { + if (operation == MinMaxOperation::Min) { return v.ir.FPVectorMin(esize, operand1, operand2); } @@ -225,7 +225,7 @@ bool FPMinMaxOperationSTS(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, return true; } -bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, MinMaxOperationSTS operation) { +bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation) { if (sz && !Q) { return v.ReservedValue(); } @@ -236,7 +236,7 @@ bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec const IR::U128 operand1 = v.V(datasize, Vn); const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { - if (operation == MinMaxOperationSTS::Min) { + if (operation == MinMaxOperation::Min) { return v.ir.FPVectorMinNumeric(esize, operand1, operand2); } @@ -247,7 +247,7 @@ bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec return true; } -bool PairedMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperationSTS operation, SignednessSTS sign) { +bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -259,14 +259,14 @@ bool PairedMinMaxOperationSTS(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, const IR::U128 operand2 = v.V(datasize, Vm); IR::U128 result = [&] { switch (operation) { - case MinMaxOperationSTS::Max: - if (sign == SignednessSTS::Signed) { + case MinMaxOperation::Max: + if (sign == Signedness::Signed) { return Q ? v.ir.VectorPairedMaxSigned(esize, operand1, operand2) : v.ir.VectorPairedMaxSignedLower(esize, operand1, operand2); } return Q ? v.ir.VectorPairedMaxUnsigned(esize, operand1, operand2) : v.ir.VectorPairedMaxUnsignedLower(esize, operand1, operand2); - case MinMaxOperationSTS::Min: - if (sign == SignednessSTS::Signed) { + case MinMaxOperation::Min: + if (sign == Signedness::Signed) { return Q ? v.ir.VectorPairedMinSigned(esize, operand1, operand2) : v.ir.VectorPairedMinSignedLower(esize, operand1, operand2); } return Q ? v.ir.VectorPairedMinUnsigned(esize, operand1, operand2) : v.ir.VectorPairedMinUnsignedLower(esize, operand1, operand2); @@ -311,7 +311,7 @@ bool FPPairedMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec V return true; } -bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, SignednessSTS sign) { +bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, Signedness sign) { if (size == 0b11 && !Q) { return v.ReservedValue(); } @@ -323,7 +323,7 @@ bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Ve const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { - if (sign == SignednessSTS::Signed) { + if (sign == Signedness::Signed) { if (op == Operation::Add) { return v.ir.VectorSignedSaturatedAdd(esize, operand1, operand2); } @@ -342,7 +342,7 @@ bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Ve return true; } -bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, SignednessSTS sign) { +bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) { if (size == 0b11 && !Q) { return v.ReservedValue(); } @@ -353,7 +353,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec const IR::U128 operand1 = v.V(datasize, Vn); const IR::U128 operand2 = v.V(datasize, Vm); const IR::U128 result = [&] { - if (sign == SignednessSTS::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2); } @@ -401,27 +401,27 @@ bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) } bool TranslatorVisitor::SABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehaviorSTS::Accumulate); + return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehavior::Accumulate); } bool TranslatorVisitor::SABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehaviorSTS::None); + return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehavior::None); } bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return VectorMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Max, SignednessSTS::Signed); + return VectorMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Signed); } bool TranslatorVisitor::SMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return PairedMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Max, SignednessSTS::Signed); + return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Signed); } bool TranslatorVisitor::SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return VectorMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Min, SignednessSTS::Signed); + return VectorMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Signed); } bool TranslatorVisitor::SMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return PairedMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Min, SignednessSTS::Signed); + return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Signed); } bool TranslatorVisitor::SQDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -506,19 +506,19 @@ bool TranslatorVisitor::MUL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, ExtraBehaviorSTS::None); + return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, ExtraBehavior::None); } bool TranslatorVisitor::RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, ExtraBehaviorSTS::Round); + return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, ExtraBehavior::Round); } bool TranslatorVisitor::SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, ExtraBehaviorSTS::None); + return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, ExtraBehavior::None); } bool TranslatorVisitor::RSUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, ExtraBehaviorSTS::Round); + return HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, ExtraBehavior::Round); } bool TranslatorVisitor::SHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -554,15 +554,15 @@ bool TranslatorVisitor::SHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, SignednessSTS::Signed); + return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, Signedness::Signed); } bool TranslatorVisitor::SQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, SignednessSTS::Signed); + return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, Signedness::Signed); } bool TranslatorVisitor::SRHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Signed); + return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::UHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -598,15 +598,15 @@ bool TranslatorVisitor::UHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::UQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, SignednessSTS::Unsigned); + return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Add, Signedness::Unsigned); } bool TranslatorVisitor::UQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, SignednessSTS::Unsigned); + return SaturatingArithmeticOperation(*this, Q, size, Vm, Vn, Vd, Operation::Subtract, Signedness::Unsigned); } bool TranslatorVisitor::URHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Unsigned); + return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -642,11 +642,11 @@ bool TranslatorVisitor::FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonTypeSTS::AbsoluteGE); + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::AbsoluteGE); } bool TranslatorVisitor::FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonTypeSTS::AbsoluteGT); + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::AbsoluteGT); } bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { @@ -737,15 +737,15 @@ bool TranslatorVisitor::FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonTypeSTS::EQ); + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ); } bool TranslatorVisitor::FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonTypeSTS::GE); + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GE); } bool TranslatorVisitor::FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonTypeSTS::GT); + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GT); } bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) { @@ -827,11 +827,11 @@ bool TranslatorVisitor::CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Signed); + return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Signed); + return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -851,11 +851,11 @@ bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::UQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Unsigned); + return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::URSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, SignednessSTS::Unsigned); + return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -875,11 +875,11 @@ bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return VectorMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Max, SignednessSTS::Unsigned); + return VectorMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Unsigned); } bool TranslatorVisitor::UMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return PairedMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Max, SignednessSTS::Unsigned); + return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Unsigned); } bool TranslatorVisitor::UABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -918,11 +918,11 @@ bool TranslatorVisitor::UABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return VectorMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Min, SignednessSTS::Unsigned); + return VectorMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Unsigned); } bool TranslatorVisitor::UMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - return PairedMinMaxOperationSTS(*this, Q, size, Vm, Vn, Vd, MinMaxOperationSTS::Min, SignednessSTS::Unsigned); + return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Unsigned); } bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { @@ -1104,11 +1104,11 @@ bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FMAX_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPMinMaxOperationSTS(*this, Q, sz, Vm, Vn, Vd, MinMaxOperationSTS::Max); + return FPMinMaxOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperation::Max); } bool TranslatorVisitor::FMAXNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPMinMaxNumericOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperationSTS::Max); + return FPMinMaxNumericOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperation::Max); } bool TranslatorVisitor::FMAXNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { @@ -1120,11 +1120,11 @@ bool TranslatorVisitor::FMAXP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FMIN_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPMinMaxOperationSTS(*this, Q, sz, Vm, Vn, Vd, MinMaxOperationSTS::Min); + return FPMinMaxOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperation::Min); } bool TranslatorVisitor::FMINNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - return FPMinMaxNumericOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperationSTS::Min); + return FPMinMaxNumericOperation(*this, Q, sz, Vm, Vn, Vd, MinMaxOperation::Min); } bool TranslatorVisitor::FMINNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp index 80a8e531a7..ca3e3b9591 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -8,7 +8,7 @@ namespace Dynarmic::A64 { namespace { -enum class ComparisonTypeSTRM { +enum class ComparisonType { EQ, GE, GT, @@ -16,7 +16,7 @@ enum class ComparisonTypeSTRM { LT, }; -bool CompareAgainstZero(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, ComparisonTypeSTRM type) { +bool CompareAgainstZero(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, ComparisonType type) { if (size == 0b11 && !Q) { return v.ReservedValue(); } @@ -28,15 +28,15 @@ bool CompareAgainstZero(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec V const IR::U128 zero = v.ir.ZeroVector(); IR::U128 result = [&] { switch (type) { - case ComparisonTypeSTRM::EQ: + case ComparisonType::EQ: return v.ir.VectorEqual(esize, operand, zero); - case ComparisonTypeSTRM::GE: + case ComparisonType::GE: return v.ir.VectorGreaterEqualSigned(esize, operand, zero); - case ComparisonTypeSTRM::GT: + case ComparisonType::GT: return v.ir.VectorGreaterSigned(esize, operand, zero); - case ComparisonTypeSTRM::LE: + case ComparisonType::LE: return v.ir.VectorLessEqualSigned(esize, operand, zero); - case ComparisonTypeSTRM::LT: + case ComparisonType::LT: default: return v.ir.VectorLessSigned(esize, operand, zero); } @@ -50,7 +50,7 @@ bool CompareAgainstZero(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec V return true; } -bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, ComparisonTypeSTRM type) { +bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, ComparisonType type) { if (sz && !Q) { return v.ReservedValue(); } @@ -62,15 +62,15 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, const IR::U128 zero = v.ir.ZeroVector(); const IR::U128 result = [&] { switch (type) { - case ComparisonTypeSTRM::EQ: + case ComparisonType::EQ: return v.ir.FPVectorEqual(esize, operand, zero); - case ComparisonTypeSTRM::GE: + case ComparisonType::GE: return v.ir.FPVectorGreaterEqual(esize, operand, zero); - case ComparisonTypeSTRM::GT: + case ComparisonType::GT: return v.ir.FPVectorGreater(esize, operand, zero); - case ComparisonTypeSTRM::LE: + case ComparisonType::LE: return v.ir.FPVectorGreaterEqual(esize, zero, operand); - case ComparisonTypeSTRM::LT: + case ComparisonType::LT: return v.ir.FPVectorGreater(esize, zero, operand); } @@ -81,12 +81,12 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, return true; } -enum class SignednessSTRM { +enum class Signedness { Signed, Unsigned }; -bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, SignednessSTRM SignednessSTRM) { +bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, Signedness signedness) { if (sz && !Q) { return v.ReservedValue(); } @@ -96,7 +96,7 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd const FP::RoundingMode rounding_mode = v.ir.current_location->FPCR().RMode(); const IR::U128 operand = v.V(datasize, Vn); - const IR::U128 result = SignednessSTRM == SignednessSTRM::Signed + const IR::U128 result = signedness == Signedness::Signed ? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode) : v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode); @@ -104,7 +104,7 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd return true; } -bool FloatConvertToInteger(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, SignednessSTRM SignednessSTRM, FP::RoundingMode rounding_mode) { +bool FloatConvertToInteger(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, Signedness signedness, FP::RoundingMode rounding_mode) { if (sz && !Q) { return v.ReservedValue(); } @@ -113,7 +113,7 @@ bool FloatConvertToInteger(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd const size_t esize = sz ? 64 : 32; const IR::U128 operand = v.V(datasize, Vn); - const IR::U128 result = SignednessSTRM == SignednessSTRM::Signed + const IR::U128 result = signedness == Signedness::Signed ? v.ir.FPVectorToSignedFixed(esize, operand, 0, rounding_mode) : v.ir.FPVectorToUnsignedFixed(esize, operand, 0, rounding_mode); @@ -168,7 +168,7 @@ enum class PairedAddLongExtraBehavior { Accumulate, }; -bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, SignednessSTRM sign, PairedAddLongExtraBehavior behavior) { +bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Signedness sign, PairedAddLongExtraBehavior behavior) { if (size == 0b11) { return v.ReservedValue(); } @@ -178,7 +178,7 @@ bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Si const IR::U128 operand = v.V(datasize, Vn); IR::U128 result = [&] { - if (sign == SignednessSTRM::Signed) { + if (sign == Signedness::Signed) { return v.ir.VectorPairedAddSignedWiden(esize, operand); } @@ -254,23 +254,23 @@ bool TranslatorVisitor::CNT(bool Q, Imm<2> size, Vec Vn, Vec Vd) { } bool TranslatorVisitor::CMGE_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonTypeSTRM::GE); + return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonType::GE); } bool TranslatorVisitor::CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonTypeSTRM::GT); + return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonType::GT); } bool TranslatorVisitor::CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonTypeSTRM::EQ); + return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonType::EQ); } bool TranslatorVisitor::CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonTypeSTRM::LE); + return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonType::LE); } bool TranslatorVisitor::CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonTypeSTRM::LT); + return CompareAgainstZero(*this, Q, size, Vn, Vd, ComparisonType::LT); } bool TranslatorVisitor::ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { @@ -341,23 +341,23 @@ bool TranslatorVisitor::FCMEQ_zero_3(bool Q, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonTypeSTRM::EQ); + return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::EQ); } bool TranslatorVisitor::FCMGE_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonTypeSTRM::GE); + return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::GE); } bool TranslatorVisitor::FCMGT_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonTypeSTRM::GT); + return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::GT); } bool TranslatorVisitor::FCMLE_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonTypeSTRM::LE); + return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::LE); } bool TranslatorVisitor::FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonTypeSTRM::LT); + return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::LT); } bool TranslatorVisitor::FCVTL(bool Q, bool sz, Vec Vn, Vec Vd) { @@ -411,19 +411,19 @@ bool TranslatorVisitor::FCVTN(bool Q, bool sz, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCVTNS_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed, FP::RoundingMode::ToNearest_TieEven); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::ToNearest_TieEven); } bool TranslatorVisitor::FCVTMS_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed, FP::RoundingMode::TowardsMinusInfinity); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::TowardsMinusInfinity); } bool TranslatorVisitor::FCVTAS_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed, FP::RoundingMode::ToNearest_TieAwayFromZero); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::ToNearest_TieAwayFromZero); } bool TranslatorVisitor::FCVTPS_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed, FP::RoundingMode::TowardsPlusInfinity); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::TowardsPlusInfinity); } bool TranslatorVisitor::FCVTXN_2(bool Q, bool sz, Vec Vn, Vec Vd) { @@ -447,27 +447,27 @@ bool TranslatorVisitor::FCVTXN_2(bool Q, bool sz, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCVTZS_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed, FP::RoundingMode::TowardsZero); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::TowardsZero); } bool TranslatorVisitor::FCVTNU_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned, FP::RoundingMode::ToNearest_TieEven); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Unsigned, FP::RoundingMode::ToNearest_TieEven); } bool TranslatorVisitor::FCVTMU_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned, FP::RoundingMode::TowardsMinusInfinity); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Unsigned, FP::RoundingMode::TowardsMinusInfinity); } bool TranslatorVisitor::FCVTAU_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned, FP::RoundingMode::ToNearest_TieAwayFromZero); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Unsigned, FP::RoundingMode::ToNearest_TieAwayFromZero); } bool TranslatorVisitor::FCVTPU_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned, FP::RoundingMode::TowardsPlusInfinity); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Unsigned, FP::RoundingMode::TowardsPlusInfinity); } bool TranslatorVisitor::FCVTZU_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatConvertToInteger(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned, FP::RoundingMode::TowardsZero); + return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Unsigned, FP::RoundingMode::TowardsZero); } bool TranslatorVisitor::FRINTN_1(bool Q, Vec Vn, Vec Vd) { @@ -780,19 +780,19 @@ bool TranslatorVisitor::USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return PairedAddLong(*this, Q, size, Vn, Vd, SignednessSTRM::Signed, PairedAddLongExtraBehavior::Accumulate); + return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate); } bool TranslatorVisitor::SADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return PairedAddLong(*this, Q, size, Vn, Vd, SignednessSTRM::Signed, PairedAddLongExtraBehavior::None); + return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::None); } bool TranslatorVisitor::UADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return PairedAddLong(*this, Q, size, Vn, Vd, SignednessSTRM::Unsigned, PairedAddLongExtraBehavior::Accumulate); + return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Unsigned, PairedAddLongExtraBehavior::Accumulate); } bool TranslatorVisitor::UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { - return PairedAddLong(*this, Q, size, Vn, Vd, SignednessSTRM::Unsigned, PairedAddLongExtraBehavior::None); + return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Unsigned, PairedAddLongExtraBehavior::None); } bool TranslatorVisitor::URECPE(bool Q, bool sz, Vec Vn, Vec Vd) { @@ -824,11 +824,11 @@ bool TranslatorVisitor::URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, SignednessSTRM::Signed); + return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::UCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { - return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, SignednessSTRM::Unsigned); + return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Unsigned); } bool TranslatorVisitor::SHLL(bool Q, Imm<2> size, Vec Vn, Vec Vd) { diff --git a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp index 1956c53acc..07234fc61b 100644 --- a/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,13 +5,13 @@ #include -#include "dynarmic/common/assert.h" +#include #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { namespace { -std::pair CombineVector(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, Imm<4> Vmlo) { +std::pair Combine(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, Imm<4> Vmlo) { if (size == 0b01) { return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend()}; } @@ -22,19 +19,19 @@ std::pair CombineVector(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, return {concatenate(H, L).ZeroExtend(), concatenate(M, Vmlo).ZeroExtend()}; } -enum class ExtraBehaviorSVXIE { +enum class ExtraBehavior { None, Extended, Accumulate, Subtract, }; -bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehaviorSVXIE extra_behavior) { +bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { if (size != 0b01 && size != 0b10) { return v.ReservedValue(); } - const auto [index, Vm] = CombineVector(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const size_t idxdsize = H == 1 ? 128 : 64; const size_t esize = 8 << size.ZeroExtend(); const size_t datasize = Q ? 128 : 64; @@ -44,9 +41,9 @@ bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm< const IR::U128 operand3 = v.V(datasize, Vd); IR::U128 result = v.ir.VectorMultiply(esize, operand1, operand2); - if (extra_behavior == ExtraBehaviorSVXIE::Accumulate) { + if (extra_behavior == ExtraBehavior::Accumulate) { result = v.ir.VectorAdd(esize, operand3, result); - } else if (extra_behavior == ExtraBehaviorSVXIE::Subtract) { + } else if (extra_behavior == ExtraBehavior::Subtract) { result = v.ir.VectorSub(esize, operand3, result); } @@ -54,7 +51,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm< return true; } -bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehaviorSVXIE extra_behavior) { +bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { if (sz && L == 1) { return v.ReservedValue(); } @@ -74,13 +71,13 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> const IR::U128 result = [&] { switch (extra_behavior) { - case ExtraBehaviorSVXIE::None: + case ExtraBehavior::None: return v.ir.FPVectorMul(esize, operand1, operand2); - case ExtraBehaviorSVXIE::Extended: + case ExtraBehavior::Extended: return v.ir.FPVectorMulX(esize, operand1, operand2); - case ExtraBehaviorSVXIE::Accumulate: + case ExtraBehavior::Accumulate: return v.ir.FPVectorMulAdd(esize, operand3, operand1, operand2); - case ExtraBehaviorSVXIE::Subtract: + case ExtraBehavior::Subtract: return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2); } UNREACHABLE(); @@ -89,7 +86,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> return true; } -bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehaviorSVXIE extra_behavior) { +bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { const size_t idxdsize = H == 1 ? 128 : 64; const size_t index = concatenate(H, L, M).ZeroExtend(); const Vec Vm = Vmlo.ZeroExtend(); @@ -104,13 +101,13 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im // regular multiplies and extended multiplies. const IR::U128 result = [&] { switch (extra_behavior) { - case ExtraBehaviorSVXIE::None: + case ExtraBehavior::None: break; - case ExtraBehaviorSVXIE::Extended: + case ExtraBehavior::Extended: break; - case ExtraBehaviorSVXIE::Accumulate: + case ExtraBehavior::Accumulate: return v.ir.FPVectorMulAdd(esize, operand3, operand1, operand2); - case ExtraBehaviorSVXIE::Subtract: + case ExtraBehavior::Subtract: return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2); } UNREACHABLE(); @@ -154,12 +151,12 @@ bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, I return true; } -enum class SignednessSVXIE { +enum class Signedness { Signed, Unsigned }; -bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehaviorSVXIE extra_behavior, SignednessSVXIE sign) { +bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior, Signedness sign) { if (size == 0b00 || size == 0b11) { return v.ReservedValue(); } @@ -167,23 +164,23 @@ bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, const size_t idxsize = H == 1 ? 128 : 64; const size_t esize = 8 << size.ZeroExtend(); const size_t datasize = 64; - const auto [index, Vm] = CombineVector(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = v.Vpart(datasize, Vn, Q); const IR::U128 operand2 = v.V(idxsize, Vm); const IR::U128 index_vector = v.ir.VectorBroadcastElement(esize, operand2, index); const IR::U128 result = [&] { - const IR::U128 product = sign == SignednessSVXIE::Signed + const IR::U128 product = sign == Signedness::Signed ? v.ir.VectorMultiplySignedWiden(esize, operand1, index_vector) : v.ir.VectorMultiplyUnsignedWiden(esize, operand1, index_vector); - if (extra_behavior == ExtraBehaviorSVXIE::None) { + if (extra_behavior == ExtraBehavior::None) { return product; } const IR::U128 operand3 = v.V(2 * datasize, Vd); - if (extra_behavior == ExtraBehaviorSVXIE::Accumulate) { + if (extra_behavior == ExtraBehavior::Accumulate) { return v.ir.VectorAdd(2 * esize, operand3, product); } @@ -196,15 +193,15 @@ bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, } // Anonymous namespace bool TranslatorVisitor::MLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Accumulate); + return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate); } bool TranslatorVisitor::MLS_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Subtract); + return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); } bool TranslatorVisitor::MUL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::None); + return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None); } bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<2> rot, Imm<1> H, Vec Vn, Vec Vd) { @@ -295,39 +292,39 @@ bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4 } bool TranslatorVisitor::FMLA_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElementHalfPrecision(*this, Q, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Accumulate); + return FPMultiplyByElementHalfPrecision(*this, Q, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate); } bool TranslatorVisitor::FMLA_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Accumulate); + return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate); } bool TranslatorVisitor::FMLS_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElementHalfPrecision(*this, Q, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Subtract); + return FPMultiplyByElementHalfPrecision(*this, Q, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); } bool TranslatorVisitor::FMLS_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Subtract); + return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); } bool TranslatorVisitor::FMUL_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::None); + return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None); } bool TranslatorVisitor::FMULX_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Extended); + return FPMultiplyByElement(*this, Q, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Extended); } bool TranslatorVisitor::SMLAL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Accumulate, SignednessSVXIE::Signed); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate, Signedness::Signed); } bool TranslatorVisitor::SMLSL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Subtract, SignednessSVXIE::Signed); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract, Signedness::Signed); } bool TranslatorVisitor::SMULL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::None, SignednessSVXIE::Signed); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None, Signedness::Signed); } bool TranslatorVisitor::SQDMULL_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { @@ -339,7 +336,7 @@ bool TranslatorVisitor::SQDMULL_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, I const size_t idxsize = H == 1 ? 128 : 64; const size_t esize = 8 << size.ZeroExtend(); const size_t datasize = 64; - const auto [index, Vm] = CombineVector(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = Vpart(datasize, Vn, part); const IR::U128 operand2 = V(idxsize, Vm); @@ -358,7 +355,7 @@ bool TranslatorVisitor::SQDMULH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, I const size_t idxsize = H == 1 ? 128 : 64; const size_t esize = 8 << size.ZeroExtend(); const size_t datasize = Q ? 128 : 64; - const auto [index, Vm] = CombineVector(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(idxsize, Vm); @@ -377,7 +374,7 @@ bool TranslatorVisitor::SQRDMULH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, const size_t idxsize = H == 1 ? 128 : 64; const size_t esize = 8 << size.ZeroExtend(); const size_t datasize = Q ? 128 : 64; - const auto [index, Vm] = CombineVector(size, H, L, M, Vmlo); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(idxsize, Vm); @@ -397,15 +394,15 @@ bool TranslatorVisitor::UDOT_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> } bool TranslatorVisitor::UMLAL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Accumulate, SignednessSVXIE::Unsigned); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate, Signedness::Unsigned); } bool TranslatorVisitor::UMLSL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::Subtract, SignednessSVXIE::Unsigned); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract, Signedness::Unsigned); } bool TranslatorVisitor::UMULL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { - return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehaviorSVXIE::None, SignednessSVXIE::Unsigned); + return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None, Signedness::Unsigned); } } // namespace Dynarmic::A64 diff --git a/externals/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h b/externals/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h index bd76efda2a..cf7d0e64bc 100644 --- a/externals/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h +++ b/externals/dynarmic/src/dynarmic/frontend/decoder/decoder_detail.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include #include diff --git a/externals/dynarmic/src/dynarmic/frontend/decoder/matcher.h b/externals/dynarmic/src/dynarmic/frontend/decoder/matcher.h index 7e5c9c5a8f..adf9556dd4 100644 --- a/externals/dynarmic/src/dynarmic/frontend/decoder/matcher.h +++ b/externals/dynarmic/src/dynarmic/frontend/decoder/matcher.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include namespace Dynarmic::Decoder { diff --git a/externals/dynarmic/src/dynarmic/frontend/imm.cpp b/externals/dynarmic/src/dynarmic/frontend/imm.cpp index 95e24206d7..c802864df9 100644 --- a/externals/dynarmic/src/dynarmic/frontend/imm.cpp +++ b/externals/dynarmic/src/dynarmic/frontend/imm.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,9 +5,9 @@ #include "dynarmic/frontend/imm.h" -#include "dynarmic/common/assert.h" +#include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic { diff --git a/externals/dynarmic/src/dynarmic/frontend/imm.h b/externals/dynarmic/src/dynarmic/frontend/imm.h index 2d529a23b8..7d86abbb61 100644 --- a/externals/dynarmic/src/dynarmic/frontend/imm.h +++ b/externals/dynarmic/src/dynarmic/frontend/imm.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,10 +7,10 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/math_util.h" diff --git a/externals/dynarmic/src/dynarmic/interface/A32/arch_version.h b/externals/dynarmic/src/dynarmic/interface/A32/arch_version.h index 209bc594f2..240e40ee4c 100644 --- a/externals/dynarmic/src/dynarmic/interface/A32/arch_version.h +++ b/externals/dynarmic/src/dynarmic/interface/A32/arch_version.h @@ -5,12 +5,10 @@ #pragma once -#include - namespace Dynarmic { namespace A32 { -enum class ArchVersion : std::uint8_t { +enum class ArchVersion { v3, v4, v4T, diff --git a/externals/dynarmic/src/dynarmic/interface/A32/config.h b/externals/dynarmic/src/dynarmic/interface/A32/config.h index 11fe2236a2..360df06e2a 100644 --- a/externals/dynarmic/src/dynarmic/interface/A32/config.h +++ b/externals/dynarmic/src/dynarmic/interface/A32/config.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -123,32 +120,14 @@ struct UserCallbacks : public TranslateCallbacks { }; struct UserConfig { - bool HasOptimization(OptimizationFlag f) const { - if (!unsafe_optimizations) { - f &= all_safe_optimizations; - } - return (f & optimizations) != no_optimizations; - } - UserCallbacks* callbacks; + size_t processor_id = 0; ExclusiveMonitor* global_monitor = nullptr; - // Page Table - // The page table is used for faster memory access. If an entry in the table is nullptr, - // the JIT will fallback to calling the MemoryRead*/MemoryWrite* callbacks. - static constexpr std::size_t PAGE_BITS = 12; - static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - PAGE_BITS); - std::array* page_table = nullptr; - - /// Coprocessors - std::array, 16> coprocessors{}; - - /// Fastmem Pointer - /// This should point to the beginning of a 4GB address space which is in arranged just like - /// what you wish for emulated memory to be. If the host page faults on an address, the JIT - /// will fallback to calling the MemoryRead*/MemoryWrite* callbacks. - std::optional fastmem_pointer = std::nullopt; + /// Select the architecture version to use. + /// There are minor behavioural differences between versions. + ArchVersion arch_version = ArchVersion::v8; /// This selects other optimizations than can't otherwise be disabled by setting other /// configuration options. This includes: @@ -158,29 +137,12 @@ struct UserConfig { /// This is intended to be used for debugging. OptimizationFlag optimizations = all_safe_optimizations; - /// Minimum size is about 8MiB. Maximum size is about 128MiB (arm64 host) or 2GiB (x64 host). - /// Maximum size is limited by the maximum length of a x86_64 / arm64 jump. - std::uint32_t code_cache_size = 128 * 1024 * 1024; // bytes - - /// Masks out the first N bits in host pointers from the page table. - /// The intention behind this is to allow users of Dynarmic to pack attributes in the - /// same integer and update the pointer attribute pair atomically. - /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes. - std::int32_t page_table_pointer_mask_bits = 0; - - /// Select the architecture version to use. - /// There are minor behavioural differences between versions. - ArchVersion arch_version = ArchVersion::v8; - - /// Processor ID - std::uint8_t processor_id = 0; - - /// Determines if we should detect memory accesses via page_table that straddle are - /// misaligned. Accesses that straddle page boundaries will fallback to the relevant - /// memory callback. - /// This value should be the required access sizes this applies to ORed together. - /// To detect any access, use: 8 | 16 | 32 | 64. - std::uint8_t detect_misaligned_access_via_page_table = 0; + bool HasOptimization(OptimizationFlag f) const { + if (!unsafe_optimizations) { + f &= all_safe_optimizations; + } + return (f & optimizations) != no_optimizations; + } /// This enables unsafe optimizations that reduce emulation accuracy in favour of speed. /// For safety, in order to enable unsafe optimizations you have to set BOTH this flag @@ -188,6 +150,12 @@ struct UserConfig { /// The prefered and tested mode for this library is with unsafe optimizations disabled. bool unsafe_optimizations = false; + // Page Table + // The page table is used for faster memory access. If an entry in the table is nullptr, + // the JIT will fallback to calling the MemoryRead*/MemoryWrite* callbacks. + static constexpr std::size_t PAGE_BITS = 12; + static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - PAGE_BITS); + std::array* page_table = nullptr; /// Determines if the pointer in the page_table shall be offseted locally or globally. /// 'false' will access page_table[addr >> bits][addr & mask] /// 'true' will access page_table[addr >> bits][addr] @@ -195,11 +163,26 @@ struct UserConfig { /// So there might be wrongly faulted pages which maps to nullptr. /// This can be avoided by carefully allocating the memory region. bool absolute_offset_page_table = false; - + /// Masks out the first N bits in host pointers from the page table. + /// The intention behind this is to allow users of Dynarmic to pack attributes in the + /// same integer and update the pointer attribute pair atomically. + /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes. + int page_table_pointer_mask_bits = 0; + /// Determines if we should detect memory accesses via page_table that straddle are + /// misaligned. Accesses that straddle page boundaries will fallback to the relevant + /// memory callback. + /// This value should be the required access sizes this applies to ORed together. + /// To detect any access, use: 8 | 16 | 32 | 64. + std::uint8_t detect_misaligned_access_via_page_table = 0; /// Determines if the above option only triggers when the misalignment straddles a /// page boundary. bool only_detect_misalignment_via_page_table_on_page_boundary = false; + // Fastmem Pointer + // This should point to the beginning of a 4GB address space which is in arranged just like + // what you wish for emulated memory to be. If the host page faults on an address, the JIT + // will fallback to calling the MemoryRead*/MemoryWrite* callbacks. + std::optional fastmem_pointer = std::nullopt; /// Determines if instructions that pagefault should cause recompilation of that block /// with fastmem disabled. /// Recompiled code will use the page_table if this is available, otherwise memory @@ -215,6 +198,9 @@ struct UserConfig { /// callbacks. bool recompile_on_exclusive_fastmem_failure = true; + // Coprocessors + std::array, 16> coprocessors{}; + /// When set to true, UserCallbacks::InstructionSynchronizationBarrierRaised will be /// called when an ISB instruction is executed. /// When set to false, ISB will be treated as a NOP instruction. @@ -248,6 +234,10 @@ struct UserConfig { /// in unusual behavior. bool always_little_endian = false; + // Minimum size is about 8MiB. Maximum size is about 128MiB (arm64 host) or 2GiB (x64 host). + // Maximum size is limited by the maximum length of a x86_64 / arm64 jump. + size_t code_cache_size = 128 * 1024 * 1024; // bytes + /// Internal use only bool very_verbose_debugging_output = false; }; diff --git a/externals/dynarmic/src/dynarmic/interface/A64/config.h b/externals/dynarmic/src/dynarmic/interface/A64/config.h index 3563c0b2f4..c8ed623eb4 100644 --- a/externals/dynarmic/src/dynarmic/interface/A64/config.h +++ b/externals/dynarmic/src/dynarmic/interface/A64/config.h @@ -136,30 +136,11 @@ struct UserCallbacks { }; struct UserConfig { - /// Fastmem Pointer - /// This should point to the beginning of a 2^page_table_address_space_bits bytes - /// address space which is in arranged just like what you wish for emulated memory to - /// be. If the host page faults on an address, the JIT will fallback to calling the - /// MemoryRead*/MemoryWrite* callbacks. - std::optional fastmem_pointer = std::nullopt; - UserCallbacks* callbacks; + size_t processor_id = 0; ExclusiveMonitor* global_monitor = nullptr; - /// Pointer to where TPIDRRO_EL0 is stored. This pointer will be inserted into - /// emitted code. - const std::uint64_t* tpidrro_el0 = nullptr; - - /// Pointer to where TPIDR_EL0 is stored. This pointer will be inserted into - /// emitted code. - std::uint64_t* tpidr_el0 = nullptr; - - /// Pointer to the page table which we can use for direct page table access. - /// If an entry in page_table is null, the relevant memory callback will be called. - /// If page_table is nullptr, all memory accesses hit the memory callbacks. - void** page_table = nullptr; - /// This selects other optimizations than can't otherwise be disabled by setting other /// configuration options. This includes: /// - IR optimizations @@ -168,50 +149,12 @@ struct UserConfig { /// This is intended to be used for debugging. OptimizationFlag optimizations = all_safe_optimizations; - /// Declares how many valid address bits are there in virtual addresses. - /// Determines the size of page_table. Valid values are between 12 and 64 inclusive. - /// This is only used if page_table is not nullptr. - std::uint32_t page_table_address_space_bits = 36; - - /// Masks out the first N bits in host pointers from the page table. - /// The intention behind this is to allow users of Dynarmic to pack attributes in the - /// same integer and update the pointer attribute pair atomically. - /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes. - std::int32_t page_table_pointer_mask_bits = 0; - - /// Counter-timer frequency register. The value of the register is not interpreted by - /// dynarmic. - std::uint32_t cntfrq_el0 = 600000000; - - /// CTR_EL0<27:24> is log2 of the cache writeback granule in words. - /// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words. - /// CTR_EL0<19:16> is log2 of the smallest data/unified cacheline in words. - /// CTR_EL0<15:14> is the level 1 instruction cache policy. - /// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words. - std::uint32_t ctr_el0 = 0x8444c004; - - /// DCZID_EL0<3:0> is log2 of the block size in words - /// DCZID_EL0<4> is 0 if the DC ZVA instruction is permitted. - std::uint32_t dczid_el0 = 4; - - /// Declares how many valid address bits are there in virtual addresses. - /// Determines the size of fastmem arena. Valid values are between 12 and 64 inclusive. - /// This is only used if fastmem_pointer is set. - std::uint32_t fastmem_address_space_bits = 36; - - // Minimum size is about 8MiB. Maximum size is about 128MiB (arm64 host) or 2GiB (x64 host). - // Maximum size is limited by the maximum length of a x86_64 / arm64 jump. - std::uint32_t code_cache_size = 128 * 1024 * 1024; // bytes - - /// Determines if we should detect memory accesses via page_table that straddle are - /// misaligned. Accesses that straddle page boundaries will fallback to the relevant - /// memory callback. - /// This value should be the required access sizes this applies to ORed together. - /// To detect any access, use: 8 | 16 | 32 | 64 | 128. - std::uint8_t detect_misaligned_access_via_page_table = 0; - - /// Processor ID - std::uint8_t processor_id = 0; + bool HasOptimization(OptimizationFlag f) const { + if (!unsafe_optimizations) { + f &= all_safe_optimizations; + } + return (f & optimizations) != no_optimizations; + } /// This enables unsafe optimizations that reduce emulation accuracy in favour of speed. /// For safety, in order to enable unsafe optimizations you have to set BOTH this flag @@ -234,13 +177,48 @@ struct UserConfig { /// instruction is executed. bool hook_hint_instructions = false; + /// Counter-timer frequency register. The value of the register is not interpreted by + /// dynarmic. + std::uint32_t cntfrq_el0 = 600000000; + + /// CTR_EL0<27:24> is log2 of the cache writeback granule in words. + /// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words. + /// CTR_EL0<19:16> is log2 of the smallest data/unified cacheline in words. + /// CTR_EL0<15:14> is the level 1 instruction cache policy. + /// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words. + std::uint32_t ctr_el0 = 0x8444c004; + + /// DCZID_EL0<3:0> is log2 of the block size in words + /// DCZID_EL0<4> is 0 if the DC ZVA instruction is permitted. + std::uint32_t dczid_el0 = 4; + + /// Pointer to where TPIDRRO_EL0 is stored. This pointer will be inserted into + /// emitted code. + const std::uint64_t* tpidrro_el0 = nullptr; + + /// Pointer to where TPIDR_EL0 is stored. This pointer will be inserted into + /// emitted code. + std::uint64_t* tpidr_el0 = nullptr; + + /// Pointer to the page table which we can use for direct page table access. + /// If an entry in page_table is null, the relevant memory callback will be called. + /// If page_table is nullptr, all memory accesses hit the memory callbacks. + void** page_table = nullptr; + /// Declares how many valid address bits are there in virtual addresses. + /// Determines the size of page_table. Valid values are between 12 and 64 inclusive. + /// This is only used if page_table is not nullptr. + size_t page_table_address_space_bits = 36; + /// Masks out the first N bits in host pointers from the page table. + /// The intention behind this is to allow users of Dynarmic to pack attributes in the + /// same integer and update the pointer attribute pair atomically. + /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes. + int page_table_pointer_mask_bits = 0; /// Determines what happens if the guest accesses an entry that is off the end of the /// page table. If true, Dynarmic will silently mirror page_table's address space. If /// false, accessing memory outside of page_table bounds will result in a call to the /// relevant memory callback. /// This is only used if page_table is not nullptr. bool silently_mirror_page_table = true; - /// Determines if the pointer in the page_table shall be offseted locally or globally. /// 'false' will access page_table[addr >> bits][addr & mask] /// 'true' will access page_table[addr >> bits][addr] @@ -248,17 +226,31 @@ struct UserConfig { /// So there might be wrongly faulted pages which maps to nullptr. /// This can be avoided by carefully allocating the memory region. bool absolute_offset_page_table = false; - + /// Determines if we should detect memory accesses via page_table that straddle are + /// misaligned. Accesses that straddle page boundaries will fallback to the relevant + /// memory callback. + /// This value should be the required access sizes this applies to ORed together. + /// To detect any access, use: 8 | 16 | 32 | 64 | 128. + std::uint8_t detect_misaligned_access_via_page_table = 0; /// Determines if the above option only triggers when the misalignment straddles a /// page boundary. bool only_detect_misalignment_via_page_table_on_page_boundary = false; + /// Fastmem Pointer + /// This should point to the beginning of a 2^page_table_address_space_bits bytes + /// address space which is in arranged just like what you wish for emulated memory to + /// be. If the host page faults on an address, the JIT will fallback to calling the + /// MemoryRead*/MemoryWrite* callbacks. + std::optional fastmem_pointer = std::nullopt; /// Determines if instructions that pagefault should cause recompilation of that block /// with fastmem disabled. /// Recompiled code will use the page_table if this is available, otherwise memory /// accesses will hit the memory callbacks. bool recompile_on_fastmem_failure = true; - + /// Declares how many valid address bits are there in virtual addresses. + /// Determines the size of fastmem arena. Valid values are between 12 and 64 inclusive. + /// This is only used if fastmem_pointer is set. + size_t fastmem_address_space_bits = 36; /// Determines what happens if the guest accesses an entry that is off the end of the /// fastmem arena. If true, Dynarmic will silently mirror fastmem's address space. If /// false, accessing memory outside of fastmem bounds will result in a call to the @@ -293,15 +285,12 @@ struct UserConfig { /// AddTicks and GetTicksRemaining are never called, and no cycle counting is done. bool enable_cycle_counting = true; + // Minimum size is about 8MiB. Maximum size is about 128MiB (arm64 host) or 2GiB (x64 host). + // Maximum size is limited by the maximum length of a x86_64 / arm64 jump. + size_t code_cache_size = 128 * 1024 * 1024; // bytes + /// Internal use only bool very_verbose_debugging_output = false; - - inline bool HasOptimization(OptimizationFlag f) const { - if (!unsafe_optimizations) { - f &= all_safe_optimizations; - } - return (f & optimizations) != no_optimizations; - } }; } // namespace A64 diff --git a/externals/dynarmic/src/dynarmic/ir/basic_block.cpp b/externals/dynarmic/src/dynarmic/ir/basic_block.cpp index 12765e26a8..c818fe0b17 100644 --- a/externals/dynarmic/src/dynarmic/ir/basic_block.cpp +++ b/externals/dynarmic/src/dynarmic/ir/basic_block.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,7 +11,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include "dynarmic/common/memory_pool.h" #include "dynarmic/frontend/A32/a32_types.h" diff --git a/externals/dynarmic/src/dynarmic/ir/basic_block.h b/externals/dynarmic/src/dynarmic/ir/basic_block.h index 45b1f4ecde..6608f0e3a2 100644 --- a/externals/dynarmic/src/dynarmic/ir/basic_block.h +++ b/externals/dynarmic/src/dynarmic/ir/basic_block.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,7 +11,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/ir/location_descriptor.h" #include "dynarmic/ir/microinstruction.h" diff --git a/externals/dynarmic/src/dynarmic/ir/ir_emitter.cpp b/externals/dynarmic/src/dynarmic/ir/ir_emitter.cpp index a8ef7e2989..fc4f69b3e0 100644 --- a/externals/dynarmic/src/dynarmic/ir/ir_emitter.cpp +++ b/externals/dynarmic/src/dynarmic/ir/ir_emitter.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,12 +7,2884 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/ir/opcodes.h" namespace Dynarmic::IR { +U1 IREmitter::Imm1(bool imm1) const { + return U1(Value(imm1)); +} + +U8 IREmitter::Imm8(u8 imm8) const { + return U8(Value(imm8)); +} + +U16 IREmitter::Imm16(u16 imm16) const { + return U16(Value(imm16)); +} + +U32 IREmitter::Imm32(u32 imm32) const { + return U32(Value(imm32)); +} + +U64 IREmitter::Imm64(u64 imm64) const { + return U64(Value(imm64)); +} + +void IREmitter::PushRSB(const LocationDescriptor& return_location) { + Inst(Opcode::PushRSB, IR::Value(return_location.Value())); +} + +U64 IREmitter::Pack2x32To1x64(const U32& lo, const U32& hi) { + return Inst(Opcode::Pack2x32To1x64, lo, hi); +} + +U128 IREmitter::Pack2x64To1x128(const U64& lo, const U64& hi) { + return Inst(Opcode::Pack2x64To1x128, lo, hi); +} + +UAny IREmitter::LeastSignificant(size_t bitsize, const U32U64& value) { + switch (bitsize) { + case 8: + return LeastSignificantByte(value); + case 16: + return LeastSignificantHalf(value); + case 32: + if (value.GetType() == Type::U32) { + return value; + } + return LeastSignificantWord(value); + case 64: + ASSERT(value.GetType() == Type::U64); + return value; + } + ASSERT_FALSE("Invalid bitsize"); +} + +U32 IREmitter::LeastSignificantWord(const U64& value) { + return Inst(Opcode::LeastSignificantWord, value); +} + +U16 IREmitter::LeastSignificantHalf(U32U64 value) { + if (value.GetType() == Type::U64) { + value = LeastSignificantWord(value); + } + return Inst(Opcode::LeastSignificantHalf, value); +} + +U8 IREmitter::LeastSignificantByte(U32U64 value) { + if (value.GetType() == Type::U64) { + value = LeastSignificantWord(value); + } + return Inst(Opcode::LeastSignificantByte, value); +} + +ResultAndCarry IREmitter::MostSignificantWord(const U64& value) { + const auto result = Inst(Opcode::MostSignificantWord, value); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +U1 IREmitter::MostSignificantBit(const U32& value) { + return Inst(Opcode::MostSignificantBit, value); +} + +U1 IREmitter::IsZero(const U32& value) { + return Inst(Opcode::IsZero32, value); +} + +U1 IREmitter::IsZero(const U64& value) { + return Inst(Opcode::IsZero64, value); +} + +U1 IREmitter::IsZero(const U32U64& value) { + if (value.GetType() == Type::U32) { + return Inst(Opcode::IsZero32, value); + } else { + return Inst(Opcode::IsZero64, value); + } +} + +U1 IREmitter::TestBit(const U32U64& value, const U8& bit) { + if (value.GetType() == Type::U32) { + return Inst(Opcode::TestBit, IndeterminateExtendToLong(value), bit); + } else { + return Inst(Opcode::TestBit, value, bit); + } +} + +U32 IREmitter::ConditionalSelect(Cond cond, const U32& a, const U32& b) { + return Inst(Opcode::ConditionalSelect32, Value{cond}, a, b); +} + +U64 IREmitter::ConditionalSelect(Cond cond, const U64& a, const U64& b) { + return Inst(Opcode::ConditionalSelect64, Value{cond}, a, b); +} + +NZCV IREmitter::ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b) { + return Inst(Opcode::ConditionalSelectNZCV, Value{cond}, a, b); +} + +U32U64 IREmitter::ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::ConditionalSelect32, Value{cond}, a, b); + } else { + return Inst(Opcode::ConditionalSelect64, Value{cond}, a, b); + } +} + +U1 IREmitter::GetCFlagFromNZCV(const NZCV& nzcv) { + return Inst(Opcode::GetCFlagFromNZCV, nzcv); +} + +NZCV IREmitter::NZCVFromPackedFlags(const U32& a) { + return Inst(Opcode::NZCVFromPackedFlags, a); +} + +NZCV IREmitter::NZCVFrom(const Value& value) { + return Inst(Opcode::GetNZCVFromOp, value); +} + +ResultAndCarry IREmitter::LogicalShiftLeft(const U32& value_in, const U8& shift_amount, const U1& carry_in) { + const auto result = Inst(Opcode::LogicalShiftLeft32, value_in, shift_amount, carry_in); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +ResultAndCarry IREmitter::LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { + const auto result = Inst(Opcode::LogicalShiftRight32, value_in, shift_amount, carry_in); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +ResultAndCarry IREmitter::ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { + const auto result = Inst(Opcode::ArithmeticShiftRight32, value_in, shift_amount, carry_in); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +ResultAndCarry IREmitter::RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { + const auto result = Inst(Opcode::RotateRight32, value_in, shift_amount, carry_in); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +ResultAndCarry IREmitter::RotateRightExtended(const U32& value_in, const U1& carry_in) { + const auto result = Inst(Opcode::RotateRightExtended, value_in, carry_in); + const auto carry_out = Inst(Opcode::GetCarryFromOp, result); + return {result, carry_out}; +} + +U32U64 IREmitter::LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount) { + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::LogicalShiftLeft32, value_in, shift_amount, Imm1(0)); + } else { + return Inst(Opcode::LogicalShiftLeft64, value_in, shift_amount); + } +} + +U32U64 IREmitter::LogicalShiftRight(const U32U64& value_in, const U8& shift_amount) { + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::LogicalShiftRight32, value_in, shift_amount, Imm1(0)); + } else { + return Inst(Opcode::LogicalShiftRight64, value_in, shift_amount); + } +} + +U32U64 IREmitter::ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount) { + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::ArithmeticShiftRight32, value_in, shift_amount, Imm1(0)); + } else { + return Inst(Opcode::ArithmeticShiftRight64, value_in, shift_amount); + } +} + +U32U64 IREmitter::RotateRight(const U32U64& value_in, const U8& shift_amount) { + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::RotateRight32, value_in, shift_amount, Imm1(0)); + } else { + return Inst(Opcode::RotateRight64, value_in, shift_amount); + } +} + +U32U64 IREmitter::LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount) { + ASSERT(value_in.GetType() == shift_amount.GetType()); + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::LogicalShiftLeftMasked32, value_in, shift_amount); + } else { + return Inst(Opcode::LogicalShiftLeftMasked64, value_in, shift_amount); + } +} + +U32U64 IREmitter::LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { + ASSERT(value_in.GetType() == shift_amount.GetType()); + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::LogicalShiftRightMasked32, value_in, shift_amount); + } else { + return Inst(Opcode::LogicalShiftRightMasked64, value_in, shift_amount); + } +} + +U32U64 IREmitter::ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { + ASSERT(value_in.GetType() == shift_amount.GetType()); + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::ArithmeticShiftRightMasked32, value_in, shift_amount); + } else { + return Inst(Opcode::ArithmeticShiftRightMasked64, value_in, shift_amount); + } +} + +U32U64 IREmitter::RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount) { + ASSERT(value_in.GetType() == shift_amount.GetType()); + if (value_in.GetType() == Type::U32) { + return Inst(Opcode::RotateRightMasked32, value_in, shift_amount); + } else { + return Inst(Opcode::RotateRightMasked64, value_in, shift_amount); + } +} + +U32U64 IREmitter::AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Add32, a, b, carry_in); + } else { + return Inst(Opcode::Add64, a, b, carry_in); + } +} + +U32U64 IREmitter::Add(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Add32, a, b, Imm1(0)); + } else { + return Inst(Opcode::Add64, a, b, Imm1(0)); + } +} + +U32U64 IREmitter::SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Sub32, a, b, carry_in); + } else { + return Inst(Opcode::Sub64, a, b, carry_in); + } +} + +U32U64 IREmitter::Sub(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Sub32, a, b, Imm1(1)); + } else { + return Inst(Opcode::Sub64, a, b, Imm1(1)); + } +} + +U32U64 IREmitter::Mul(const U32U64& a, const U32U64& b) { + if (a.GetType() == Type::U32) { + return Inst(Opcode::Mul32, a, b); + } + + return Inst(Opcode::Mul64, a, b); +} + +U64 IREmitter::UnsignedMultiplyHigh(const U64& a, const U64& b) { + return Inst(Opcode::UnsignedMultiplyHigh64, a, b); +} + +U64 IREmitter::SignedMultiplyHigh(const U64& a, const U64& b) { + return Inst(Opcode::SignedMultiplyHigh64, a, b); +} + +U32U64 IREmitter::UnsignedDiv(const U32U64& a, const U32U64& b) { + if (a.GetType() == Type::U32) { + return Inst(Opcode::UnsignedDiv32, a, b); + } + + return Inst(Opcode::UnsignedDiv64, a, b); +} + +U32U64 IREmitter::SignedDiv(const U32U64& a, const U32U64& b) { + if (a.GetType() == Type::U32) { + return Inst(Opcode::SignedDiv32, a, b); + } + + return Inst(Opcode::SignedDiv64, a, b); +} + +U32U64 IREmitter::And(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::And32, a, b); + } else { + return Inst(Opcode::And64, a, b); + } +} + +U32U64 IREmitter::AndNot(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::AndNot32, a, b); + } else { + return Inst(Opcode::AndNot64, a, b); + } +} + +U32U64 IREmitter::Eor(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Eor32, a, b); + } else { + return Inst(Opcode::Eor64, a, b); + } +} + +U32U64 IREmitter::Or(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + if (a.GetType() == Type::U32) { + return Inst(Opcode::Or32, a, b); + } else { + return Inst(Opcode::Or64, a, b); + } +} + +U32U64 IREmitter::Not(const U32U64& a) { + if (a.GetType() == Type::U32) { + return Inst(Opcode::Not32, a); + } else { + return Inst(Opcode::Not64, a); + } +} + +U64 IREmitter::SignExtendToLong(const UAny& a) { + switch (a.GetType()) { + case Type::U8: + return Inst(Opcode::SignExtendByteToLong, a); + case Type::U16: + return Inst(Opcode::SignExtendHalfToLong, a); + case Type::U32: + return Inst(Opcode::SignExtendWordToLong, a); + case Type::U64: + return U64(a); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::SignExtendToWord(const UAny& a) { + switch (a.GetType()) { + case Type::U8: + return Inst(Opcode::SignExtendByteToWord, a); + case Type::U16: + return Inst(Opcode::SignExtendHalfToWord, a); + case Type::U32: + return U32(a); + case Type::U64: + return Inst(Opcode::LeastSignificantWord, a); + default: + UNREACHABLE(); + } +} + +U64 IREmitter::SignExtendWordToLong(const U32& a) { + return Inst(Opcode::SignExtendWordToLong, a); +} + +U32 IREmitter::SignExtendHalfToWord(const U16& a) { + return Inst(Opcode::SignExtendHalfToWord, a); +} + +U32 IREmitter::SignExtendByteToWord(const U8& a) { + return Inst(Opcode::SignExtendByteToWord, a); +} + +U64 IREmitter::ZeroExtendToLong(const UAny& a) { + switch (a.GetType()) { + case Type::U8: + return Inst(Opcode::ZeroExtendByteToLong, a); + case Type::U16: + return Inst(Opcode::ZeroExtendHalfToLong, a); + case Type::U32: + return Inst(Opcode::ZeroExtendWordToLong, a); + case Type::U64: + return U64(a); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::ZeroExtendToWord(const UAny& a) { + switch (a.GetType()) { + case Type::U8: + return Inst(Opcode::ZeroExtendByteToWord, a); + case Type::U16: + return Inst(Opcode::ZeroExtendHalfToWord, a); + case Type::U32: + return U32(a); + case Type::U64: + return Inst(Opcode::LeastSignificantWord, a); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::ZeroExtendToQuad(const UAny& a) { + return Inst(Opcode::ZeroExtendLongToQuad, ZeroExtendToLong(a)); +} + +U64 IREmitter::ZeroExtendWordToLong(const U32& a) { + return Inst(Opcode::ZeroExtendWordToLong, a); +} + +U32 IREmitter::ZeroExtendHalfToWord(const U16& a) { + return Inst(Opcode::ZeroExtendHalfToWord, a); +} + +U32 IREmitter::ZeroExtendByteToWord(const U8& a) { + return Inst(Opcode::ZeroExtendByteToWord, a); +} + +U32 IREmitter::IndeterminateExtendToWord(const UAny& a) { + // TODO: Implement properly + return ZeroExtendToWord(a); +} + +U64 IREmitter::IndeterminateExtendToLong(const UAny& a) { + // TODO: Implement properly + return ZeroExtendToLong(a); +} + +U32 IREmitter::ByteReverseWord(const U32& a) { + return Inst(Opcode::ByteReverseWord, a); +} + +U16 IREmitter::ByteReverseHalf(const U16& a) { + return Inst(Opcode::ByteReverseHalf, a); +} + +U64 IREmitter::ByteReverseDual(const U64& a) { + return Inst(Opcode::ByteReverseDual, a); +} + +U32U64 IREmitter::CountLeadingZeros(const U32U64& a) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::CountLeadingZeros32, a); + } + + return Inst(Opcode::CountLeadingZeros64, a); +} + +U32U64 IREmitter::ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::ExtractRegister32, a, b, lsb); + } + + return Inst(Opcode::ExtractRegister64, a, b, lsb); +} + +U32U64 IREmitter::ReplicateBit(const U32U64& a, u8 bit) { + if (a.GetType() == IR::Type::U32) { + ASSERT(bit < 32); + return Inst(Opcode::ReplicateBit32, a, Imm8(bit)); + } + + ASSERT(bit < 64); + return Inst(Opcode::ReplicateBit64, a, Imm8(bit)); +} + +U32U64 IREmitter::MaxSigned(const U32U64& a, const U32U64& b) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::MaxSigned32, a, b); + } + + return Inst(Opcode::MaxSigned64, a, b); +} + +U32U64 IREmitter::MaxUnsigned(const U32U64& a, const U32U64& b) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::MaxUnsigned32, a, b); + } + + return Inst(Opcode::MaxUnsigned64, a, b); +} + +U32U64 IREmitter::MinSigned(const U32U64& a, const U32U64& b) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::MinSigned32, a, b); + } + + return Inst(Opcode::MinSigned64, a, b); +} + +U32U64 IREmitter::MinUnsigned(const U32U64& a, const U32U64& b) { + if (a.GetType() == IR::Type::U32) { + return Inst(Opcode::MinUnsigned32, a, b); + } + + return Inst(Opcode::MinUnsigned64, a, b); +} + +ResultAndOverflow IREmitter::SignedSaturatedAddWithFlag(const U32& a, const U32& b) { + const auto result = Inst(Opcode::SignedSaturatedAddWithFlag32, a, b); + const auto overflow = Inst(Opcode::GetOverflowFromOp, result); + return {result, overflow}; +} + +ResultAndOverflow IREmitter::SignedSaturatedSubWithFlag(const U32& a, const U32& b) { + const auto result = Inst(Opcode::SignedSaturatedSubWithFlag32, a, b); + const auto overflow = Inst(Opcode::GetOverflowFromOp, result); + return {result, overflow}; +} + +ResultAndOverflow IREmitter::SignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { + ASSERT(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32); + const auto result = Inst(Opcode::SignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); + const auto overflow = Inst(Opcode::GetOverflowFromOp, result); + return {result, overflow}; +} + +ResultAndOverflow IREmitter::UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { + ASSERT(bit_size_to_saturate_to <= 31); + const auto result = Inst(Opcode::UnsignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); + const auto overflow = Inst(Opcode::GetOverflowFromOp, result); + return {result, overflow}; +} + +UAny IREmitter::SignedSaturatedAdd(const UAny& a, const UAny& b) { + ASSERT(a.GetType() == b.GetType()); + const auto result = [&]() -> IR::UAny { + switch (a.GetType()) { + case IR::Type::U8: + return Inst(Opcode::SignedSaturatedAdd8, a, b); + case IR::Type::U16: + return Inst(Opcode::SignedSaturatedAdd16, a, b); + case IR::Type::U32: + return Inst(Opcode::SignedSaturatedAdd32, a, b); + case IR::Type::U64: + return Inst(Opcode::SignedSaturatedAdd64, a, b); + default: + return IR::UAny{}; + } + }(); + return result; +} + +UAny IREmitter::SignedSaturatedDoublingMultiplyReturnHigh(const UAny& a, const UAny& b) { + ASSERT(a.GetType() == b.GetType()); + const auto result = [&]() -> IR::UAny { + switch (a.GetType()) { + case IR::Type::U16: + return Inst(Opcode::SignedSaturatedDoublingMultiplyReturnHigh16, a, b); + case IR::Type::U32: + return Inst(Opcode::SignedSaturatedDoublingMultiplyReturnHigh32, a, b); + default: + UNREACHABLE(); + } + }(); + return result; +} + +UAny IREmitter::SignedSaturatedSub(const UAny& a, const UAny& b) { + ASSERT(a.GetType() == b.GetType()); + const auto result = [&]() -> IR::UAny { + switch (a.GetType()) { + case IR::Type::U8: + return Inst(Opcode::SignedSaturatedSub8, a, b); + case IR::Type::U16: + return Inst(Opcode::SignedSaturatedSub16, a, b); + case IR::Type::U32: + return Inst(Opcode::SignedSaturatedSub32, a, b); + case IR::Type::U64: + return Inst(Opcode::SignedSaturatedSub64, a, b); + default: + return IR::UAny{}; + } + }(); + return result; +} + +UAny IREmitter::UnsignedSaturatedAdd(const UAny& a, const UAny& b) { + ASSERT(a.GetType() == b.GetType()); + const auto result = [&]() -> IR::UAny { + switch (a.GetType()) { + case IR::Type::U8: + return Inst(Opcode::UnsignedSaturatedAdd8, a, b); + case IR::Type::U16: + return Inst(Opcode::UnsignedSaturatedAdd16, a, b); + case IR::Type::U32: + return Inst(Opcode::UnsignedSaturatedAdd32, a, b); + case IR::Type::U64: + return Inst(Opcode::UnsignedSaturatedAdd64, a, b); + default: + return IR::UAny{}; + } + }(); + return result; +} + +UAny IREmitter::UnsignedSaturatedSub(const UAny& a, const UAny& b) { + ASSERT(a.GetType() == b.GetType()); + const auto result = [&]() -> IR::UAny { + switch (a.GetType()) { + case IR::Type::U8: + return Inst(Opcode::UnsignedSaturatedSub8, a, b); + case IR::Type::U16: + return Inst(Opcode::UnsignedSaturatedSub16, a, b); + case IR::Type::U32: + return Inst(Opcode::UnsignedSaturatedSub32, a, b); + case IR::Type::U64: + return Inst(Opcode::UnsignedSaturatedSub64, a, b); + default: + return IR::UAny{}; + } + }(); + return result; +} + +U128 IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedAdd8, a, b); + case 16: + return Inst(Opcode::VectorSignedSaturatedAdd16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedAdd32, a, b); + case 64: + return Inst(Opcode::VectorSignedSaturatedAdd64, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedSub8, a, b); + case 16: + return Inst(Opcode::VectorSignedSaturatedSub16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedSub32, a, b); + case 64: + return Inst(Opcode::VectorSignedSaturatedSub64, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorUnsignedSaturatedAdd8, a, b); + case 16: + return Inst(Opcode::VectorUnsignedSaturatedAdd16, a, b); + case 32: + return Inst(Opcode::VectorUnsignedSaturatedAdd32, a, b); + case 64: + return Inst(Opcode::VectorUnsignedSaturatedAdd64, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorUnsignedSaturatedSub8, a, b); + case 16: + return Inst(Opcode::VectorUnsignedSaturatedSub16, a, b); + case 32: + return Inst(Opcode::VectorUnsignedSaturatedSub32, a, b); + case 64: + return Inst(Opcode::VectorUnsignedSaturatedSub64, a, b); + default: + UNREACHABLE(); + } +} + +ResultAndGE IREmitter::PackedAddU8(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddU8, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedAddS8(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddS8, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedAddU16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddU16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedAddS16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddS16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubU8(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubU8, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubS8(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubS8, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubU16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubU16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubS16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubS16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedAddSubU16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddSubU16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedAddSubS16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedAddSubS16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubAddU16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubAddU16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +ResultAndGE IREmitter::PackedSubAddS16(const U32& a, const U32& b) { + const auto result = Inst(Opcode::PackedSubAddS16, a, b); + const auto ge = Inst(Opcode::GetGEFromOp, result); + return {result, ge}; +} + +U32 IREmitter::PackedHalvingAddU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddU8, a, b); +} + +U32 IREmitter::PackedHalvingAddS8(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddS8, a, b); +} + +U32 IREmitter::PackedHalvingSubU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubU8, a, b); +} + +U32 IREmitter::PackedHalvingSubS8(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubS8, a, b); +} + +U32 IREmitter::PackedHalvingAddU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddU16, a, b); +} + +U32 IREmitter::PackedHalvingAddS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddS16, a, b); +} + +U32 IREmitter::PackedHalvingSubU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubU16, a, b); +} + +U32 IREmitter::PackedHalvingSubS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubS16, a, b); +} + +U32 IREmitter::PackedHalvingAddSubU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddSubU16, a, b); +} + +U32 IREmitter::PackedHalvingAddSubS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingAddSubS16, a, b); +} + +U32 IREmitter::PackedHalvingSubAddU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubAddU16, a, b); +} + +U32 IREmitter::PackedHalvingSubAddS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedHalvingSubAddS16, a, b); +} + +U32 IREmitter::PackedSaturatedAddU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedAddU8, a, b); +} + +U32 IREmitter::PackedSaturatedAddS8(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedAddS8, a, b); +} + +U32 IREmitter::PackedSaturatedSubU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedSubU8, a, b); +} + +U32 IREmitter::PackedSaturatedSubS8(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedSubS8, a, b); +} + +U32 IREmitter::PackedSaturatedAddU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedAddU16, a, b); +} + +U32 IREmitter::PackedSaturatedAddS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedAddS16, a, b); +} + +U32 IREmitter::PackedSaturatedSubU16(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedSubU16, a, b); +} + +U32 IREmitter::PackedSaturatedSubS16(const U32& a, const U32& b) { + return Inst(Opcode::PackedSaturatedSubS16, a, b); +} + +U32 IREmitter::PackedAbsDiffSumU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedAbsDiffSumU8, a, b); +} + +U32 IREmitter::PackedSelect(const U32& ge, const U32& a, const U32& b) { + return Inst(Opcode::PackedSelect, ge, a, b); +} + +U32 IREmitter::CRC32Castagnoli8(const U32& a, const U32& b) { + return Inst(Opcode::CRC32Castagnoli8, a, b); +} + +U32 IREmitter::CRC32Castagnoli16(const U32& a, const U32& b) { + return Inst(Opcode::CRC32Castagnoli16, a, b); +} + +U32 IREmitter::CRC32Castagnoli32(const U32& a, const U32& b) { + return Inst(Opcode::CRC32Castagnoli32, a, b); +} + +U32 IREmitter::CRC32Castagnoli64(const U32& a, const U64& b) { + return Inst(Opcode::CRC32Castagnoli64, a, b); +} + +U32 IREmitter::CRC32ISO8(const U32& a, const U32& b) { + return Inst(Opcode::CRC32ISO8, a, b); +} + +U32 IREmitter::CRC32ISO16(const U32& a, const U32& b) { + return Inst(Opcode::CRC32ISO16, a, b); +} + +U32 IREmitter::CRC32ISO32(const U32& a, const U32& b) { + return Inst(Opcode::CRC32ISO32, a, b); +} + +U32 IREmitter::CRC32ISO64(const U32& a, const U64& b) { + return Inst(Opcode::CRC32ISO64, a, b); +} + +U128 IREmitter::AESDecryptSingleRound(const U128& a) { + return Inst(Opcode::AESDecryptSingleRound, a); +} + +U128 IREmitter::AESEncryptSingleRound(const U128& a) { + return Inst(Opcode::AESEncryptSingleRound, a); +} + +U128 IREmitter::AESInverseMixColumns(const U128& a) { + return Inst(Opcode::AESInverseMixColumns, a); +} + +U128 IREmitter::AESMixColumns(const U128& a) { + return Inst(Opcode::AESMixColumns, a); +} + +U8 IREmitter::SM4AccessSubstitutionBox(const U8& a) { + return Inst(Opcode::SM4AccessSubstitutionBox, a); +} + +U128 IREmitter::SHA256Hash(const U128& x, const U128& y, const U128& w, bool part1) { + return Inst(Opcode::SHA256Hash, x, y, w, Imm1(part1)); +} + +U128 IREmitter::SHA256MessageSchedule0(const U128& x, const U128& y) { + return Inst(Opcode::SHA256MessageSchedule0, x, y); +} + +U128 IREmitter::SHA256MessageSchedule1(const U128& x, const U128& y, const U128& z) { + return Inst(Opcode::SHA256MessageSchedule1, x, y, z); +} + +UAny IREmitter::VectorGetElement(size_t esize, const U128& a, size_t index) { + ASSERT_MSG(esize * index < 128, "Invalid index"); + switch (esize) { + case 8: + return Inst(Opcode::VectorGetElement8, a, Imm8(static_cast(index))); + case 16: + return Inst(Opcode::VectorGetElement16, a, Imm8(static_cast(index))); + case 32: + return Inst(Opcode::VectorGetElement32, a, Imm8(static_cast(index))); + case 64: + return Inst(Opcode::VectorGetElement64, a, Imm8(static_cast(index))); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorSetElement(size_t esize, const U128& a, size_t index, const IR::UAny& elem) { + ASSERT_MSG(esize * index < 128, "Invalid index"); + switch (esize) { + case 8: + return Inst(Opcode::VectorSetElement8, a, Imm8(static_cast(index)), elem); + case 16: + return Inst(Opcode::VectorSetElement16, a, Imm8(static_cast(index)), elem); + case 32: + return Inst(Opcode::VectorSetElement32, a, Imm8(static_cast(index)), elem); + case 64: + return Inst(Opcode::VectorSetElement64, a, Imm8(static_cast(index)), elem); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorAbs(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorAbs8, a); + case 16: + return Inst(Opcode::VectorAbs16, a); + case 32: + return Inst(Opcode::VectorAbs32, a); + case 64: + return Inst(Opcode::VectorAbs64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorAdd(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorAdd8, a, b); + case 16: + return Inst(Opcode::VectorAdd16, a, b); + case 32: + return Inst(Opcode::VectorAdd32, a, b); + case 64: + return Inst(Opcode::VectorAdd64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorAnd(const U128& a, const U128& b) { + return Inst(Opcode::VectorAnd, a, b); +} + +U128 IREmitter::VectorAndNot(const U128& a, const U128& b) { + return Inst(Opcode::VectorAndNot, a, b); +} + +U128 IREmitter::VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount) { + switch (esize) { + case 8: + return Inst(Opcode::VectorArithmeticShiftRight8, a, Imm8(shift_amount)); + case 16: + return Inst(Opcode::VectorArithmeticShiftRight16, a, Imm8(shift_amount)); + case 32: + return Inst(Opcode::VectorArithmeticShiftRight32, a, Imm8(shift_amount)); + case 64: + return Inst(Opcode::VectorArithmeticShiftRight64, a, Imm8(shift_amount)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorArithmeticVShift8, a, b); + case 16: + return Inst(Opcode::VectorArithmeticVShift16, a, b); + case 32: + return Inst(Opcode::VectorArithmeticVShift32, a, b); + case 64: + return Inst(Opcode::VectorArithmeticVShift64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorBroadcastLower(size_t esize, const UAny& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorBroadcastLower8, U8(a)); + case 16: + return Inst(Opcode::VectorBroadcastLower16, U16(a)); + case 32: + return Inst(Opcode::VectorBroadcastLower32, U32(a)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorBroadcast(size_t esize, const UAny& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorBroadcast8, U8(a)); + case 16: + return Inst(Opcode::VectorBroadcast16, U16(a)); + case 32: + return Inst(Opcode::VectorBroadcast32, U32(a)); + case 64: + return Inst(Opcode::VectorBroadcast64, U64(a)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) { + ASSERT_MSG(esize * index < 128, "Invalid index"); + switch (esize) { + case 8: + return Inst(Opcode::VectorBroadcastElementLower8, a, u8(index)); + case 16: + return Inst(Opcode::VectorBroadcastElementLower16, a, u8(index)); + case 32: + return Inst(Opcode::VectorBroadcastElementLower32, a, u8(index)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorBroadcastElement(size_t esize, const U128& a, size_t index) { + ASSERT_MSG(esize * index < 128, "Invalid index"); + switch (esize) { + case 8: + return Inst(Opcode::VectorBroadcastElement8, a, u8(index)); + case 16: + return Inst(Opcode::VectorBroadcastElement16, a, u8(index)); + case 32: + return Inst(Opcode::VectorBroadcastElement32, a, u8(index)); + case 64: + return Inst(Opcode::VectorBroadcastElement64, a, u8(index)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorCountLeadingZeros(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorCountLeadingZeros8, a); + case 16: + return Inst(Opcode::VectorCountLeadingZeros16, a); + case 32: + return Inst(Opcode::VectorCountLeadingZeros32, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorDeinterleaveEven8, a, b); + case 16: + return Inst(Opcode::VectorDeinterleaveEven16, a, b); + case 32: + return Inst(Opcode::VectorDeinterleaveEven32, a, b); + case 64: + return Inst(Opcode::VectorDeinterleaveEven64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorDeinterleaveOdd8, a, b); + case 16: + return Inst(Opcode::VectorDeinterleaveOdd16, a, b); + case 32: + return Inst(Opcode::VectorDeinterleaveOdd32, a, b); + case 64: + return Inst(Opcode::VectorDeinterleaveOdd64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorDeinterleaveEvenLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorDeinterleaveEvenLower8, a, b); + case 16: + return Inst(Opcode::VectorDeinterleaveEvenLower16, a, b); + case 32: + return Inst(Opcode::VectorDeinterleaveEvenLower32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorDeinterleaveOddLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorDeinterleaveOddLower8, a, b); + case 16: + return Inst(Opcode::VectorDeinterleaveOddLower16, a, b); + case 32: + return Inst(Opcode::VectorDeinterleaveOddLower32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorEor(const U128& a, const U128& b) { + return Inst(Opcode::VectorEor, a, b); +} + +U128 IREmitter::VectorEqual(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorEqual8, a, b); + case 16: + return Inst(Opcode::VectorEqual16, a, b); + case 32: + return Inst(Opcode::VectorEqual32, a, b); + case 64: + return Inst(Opcode::VectorEqual64, a, b); + case 128: + return Inst(Opcode::VectorEqual128, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorExtract(const U128& a, const U128& b, size_t position) { + ASSERT(position <= 128); + return Inst(Opcode::VectorExtract, a, b, Imm8(static_cast(position))); +} + +U128 IREmitter::VectorExtractLower(const U128& a, const U128& b, size_t position) { + ASSERT(position <= 64); + return Inst(Opcode::VectorExtractLower, a, b, Imm8(static_cast(position))); +} + +U128 IREmitter::VectorGreaterSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorGreaterS8, a, b); + case 16: + return Inst(Opcode::VectorGreaterS16, a, b); + case 32: + return Inst(Opcode::VectorGreaterS32, a, b); + case 64: + return Inst(Opcode::VectorGreaterS64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b) { + return VectorOr(VectorGreaterSigned(esize, a, b), VectorEqual(esize, a, b)); +} + +U128 IREmitter::VectorGreaterEqualUnsigned(size_t esize, const U128& a, const U128& b) { + return VectorEqual(esize, VectorMaxUnsigned(esize, a, b), a); +} + +U128 IREmitter::VectorGreaterUnsigned(size_t esize, const U128& a, const U128& b) { + return VectorNot(VectorEqual(esize, VectorMinUnsigned(esize, a, b), a)); +} + +U128 IREmitter::VectorHalvingAddSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorHalvingAddS8, a, b); + case 16: + return Inst(Opcode::VectorHalvingAddS16, a, b); + case 32: + return Inst(Opcode::VectorHalvingAddS32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorHalvingAddU8, a, b); + case 16: + return Inst(Opcode::VectorHalvingAddU16, a, b); + case 32: + return Inst(Opcode::VectorHalvingAddU32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorHalvingSubS8, a, b); + case 16: + return Inst(Opcode::VectorHalvingSubS16, a, b); + case 32: + return Inst(Opcode::VectorHalvingSubS32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorHalvingSubU8, a, b); + case 16: + return Inst(Opcode::VectorHalvingSubU16, a, b); + case 32: + return Inst(Opcode::VectorHalvingSubU32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorInterleaveLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorInterleaveLower8, a, b); + case 16: + return Inst(Opcode::VectorInterleaveLower16, a, b); + case 32: + return Inst(Opcode::VectorInterleaveLower32, a, b); + case 64: + return Inst(Opcode::VectorInterleaveLower64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorInterleaveUpper(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorInterleaveUpper8, a, b); + case 16: + return Inst(Opcode::VectorInterleaveUpper16, a, b); + case 32: + return Inst(Opcode::VectorInterleaveUpper32, a, b); + case 64: + return Inst(Opcode::VectorInterleaveUpper64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorLessEqualSigned(size_t esize, const U128& a, const U128& b) { + return VectorNot(VectorGreaterSigned(esize, a, b)); +} + +U128 IREmitter::VectorLessEqualUnsigned(size_t esize, const U128& a, const U128& b) { + return VectorEqual(esize, VectorMinUnsigned(esize, a, b), a); +} + +U128 IREmitter::VectorLessSigned(size_t esize, const U128& a, const U128& b) { + return VectorNot(VectorOr(VectorGreaterSigned(esize, a, b), VectorEqual(esize, a, b))); +} + +U128 IREmitter::VectorLessUnsigned(size_t esize, const U128& a, const U128& b) { + return VectorNot(VectorEqual(esize, VectorMaxUnsigned(esize, a, b), a)); +} + +U128 IREmitter::VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount) { + switch (esize) { + case 8: + return Inst(Opcode::VectorLogicalShiftLeft8, a, Imm8(shift_amount)); + case 16: + return Inst(Opcode::VectorLogicalShiftLeft16, a, Imm8(shift_amount)); + case 32: + return Inst(Opcode::VectorLogicalShiftLeft32, a, Imm8(shift_amount)); + case 64: + return Inst(Opcode::VectorLogicalShiftLeft64, a, Imm8(shift_amount)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) { + switch (esize) { + case 8: + return Inst(Opcode::VectorLogicalShiftRight8, a, Imm8(shift_amount)); + case 16: + return Inst(Opcode::VectorLogicalShiftRight16, a, Imm8(shift_amount)); + case 32: + return Inst(Opcode::VectorLogicalShiftRight32, a, Imm8(shift_amount)); + case 64: + return Inst(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorLogicalVShift(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorLogicalVShift8, a, b); + case 16: + return Inst(Opcode::VectorLogicalVShift16, a, b); + case 32: + return Inst(Opcode::VectorLogicalVShift32, a, b); + case 64: + return Inst(Opcode::VectorLogicalVShift64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMaxSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMaxS8, a, b); + case 16: + return Inst(Opcode::VectorMaxS16, a, b); + case 32: + return Inst(Opcode::VectorMaxS32, a, b); + case 64: + return Inst(Opcode::VectorMaxS64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMaxU8, a, b); + case 16: + return Inst(Opcode::VectorMaxU16, a, b); + case 32: + return Inst(Opcode::VectorMaxU32, a, b); + case 64: + return Inst(Opcode::VectorMaxU64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMinSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMinS8, a, b); + case 16: + return Inst(Opcode::VectorMinS16, a, b); + case 32: + return Inst(Opcode::VectorMinS32, a, b); + case 64: + return Inst(Opcode::VectorMinS64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMinUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMinU8, a, b); + case 16: + return Inst(Opcode::VectorMinU16, a, b); + case 32: + return Inst(Opcode::VectorMinU32, a, b); + case 64: + return Inst(Opcode::VectorMinU64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMultiply(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMultiply8, a, b); + case 16: + return Inst(Opcode::VectorMultiply16, a, b); + case 32: + return Inst(Opcode::VectorMultiply32, a, b); + case 64: + return Inst(Opcode::VectorMultiply64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMultiplySignedWiden(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMultiplySignedWiden8, a, b); + case 16: + return Inst(Opcode::VectorMultiplySignedWiden16, a, b); + case 32: + return Inst(Opcode::VectorMultiplySignedWiden32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorMultiplyUnsignedWiden(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorMultiplyUnsignedWiden8, a, b); + case 16: + return Inst(Opcode::VectorMultiplyUnsignedWiden16, a, b); + case 32: + return Inst(Opcode::VectorMultiplyUnsignedWiden32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorNarrow(size_t original_esize, const U128& a) { + switch (original_esize) { + case 16: + return Inst(Opcode::VectorNarrow16, a); + case 32: + return Inst(Opcode::VectorNarrow32, a); + case 64: + return Inst(Opcode::VectorNarrow64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorNot(const U128& a) { + return Inst(Opcode::VectorNot, a); +} + +U128 IREmitter::VectorOr(const U128& a, const U128& b) { + return Inst(Opcode::VectorOr, a, b); +} + +U128 IREmitter::VectorPairedAdd(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedAdd8, a, b); + case 16: + return Inst(Opcode::VectorPairedAdd16, a, b); + case 32: + return Inst(Opcode::VectorPairedAdd32, a, b); + case 64: + return Inst(Opcode::VectorPairedAdd64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorPairedAddLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedAddLower8, a, b); + case 16: + return Inst(Opcode::VectorPairedAddLower16, a, b); + case 32: + return Inst(Opcode::VectorPairedAddLower32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorPairedAddSignedWiden(size_t original_esize, const U128& a) { + switch (original_esize) { + case 8: + return Inst(Opcode::VectorPairedAddSignedWiden8, a); + case 16: + return Inst(Opcode::VectorPairedAddSignedWiden16, a); + case 32: + return Inst(Opcode::VectorPairedAddSignedWiden32, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a) { + switch (original_esize) { + case 8: + return Inst(Opcode::VectorPairedAddUnsignedWiden8, a); + case 16: + return Inst(Opcode::VectorPairedAddUnsignedWiden16, a); + case 32: + return Inst(Opcode::VectorPairedAddUnsignedWiden32, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMaxS8, a, b); + case 16: + return Inst(Opcode::VectorPairedMaxS16, a, b); + case 32: + return Inst(Opcode::VectorPairedMaxS32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMaxUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMaxU8, a, b); + case 16: + return Inst(Opcode::VectorPairedMaxU16, a, b); + case 32: + return Inst(Opcode::VectorPairedMaxU32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMinSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMinS8, a, b); + case 16: + return Inst(Opcode::VectorPairedMinS16, a, b); + case 32: + return Inst(Opcode::VectorPairedMinS32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMinUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMinU8, a, b); + case 16: + return Inst(Opcode::VectorPairedMinU16, a, b); + case 32: + return Inst(Opcode::VectorPairedMinU32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMaxSignedLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMaxLowerS8, a, b); + case 16: + return Inst(Opcode::VectorPairedMaxLowerS16, a, b); + case 32: + return Inst(Opcode::VectorPairedMaxLowerS32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMaxUnsignedLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMaxLowerU8, a, b); + case 16: + return Inst(Opcode::VectorPairedMaxLowerU16, a, b); + case 32: + return Inst(Opcode::VectorPairedMaxLowerU32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMinSignedLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMinLowerS8, a, b); + case 16: + return Inst(Opcode::VectorPairedMinLowerS16, a, b); + case 32: + return Inst(Opcode::VectorPairedMinLowerS32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPairedMinUnsignedLower(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPairedMinLowerU8, a, b); + case 16: + return Inst(Opcode::VectorPairedMinLowerU16, a, b); + case 32: + return Inst(Opcode::VectorPairedMinLowerU32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPolynomialMultiply(const U128& a, const U128& b) { + return Inst(Opcode::VectorPolynomialMultiply8, a, b); +} + +U128 IREmitter::VectorPolynomialMultiplyLong(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorPolynomialMultiplyLong8, a, b); + case 64: + return Inst(Opcode::VectorPolynomialMultiplyLong64, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorPopulationCount(const U128& a) { + return Inst(Opcode::VectorPopulationCount, a); +} + +U128 IREmitter::VectorReverseBits(const U128& a) { + return Inst(Opcode::VectorReverseBits, a); +} + +U128 IREmitter::VectorReverseElementsInHalfGroups(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorReverseElementsInHalfGroups8, a); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorReverseElementsInWordGroups(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorReverseElementsInWordGroups8, a); + case 16: + return Inst(Opcode::VectorReverseElementsInWordGroups16, a); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorReverseElementsInLongGroups(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorReverseElementsInLongGroups8, a); + case 16: + return Inst(Opcode::VectorReverseElementsInLongGroups16, a); + case 32: + return Inst(Opcode::VectorReverseElementsInLongGroups32, a); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorReduceAdd(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorReduceAdd8, a); + case 16: + return Inst(Opcode::VectorReduceAdd16, a); + case 32: + return Inst(Opcode::VectorReduceAdd32, a); + case 64: + return Inst(Opcode::VectorReduceAdd64, a); + } + + UNREACHABLE(); +} + +U128 IREmitter::VectorRotateLeft(size_t esize, const U128& a, u8 amount) { + ASSERT(amount < esize); + + if (amount == 0) { + return a; + } + + return VectorOr(VectorLogicalShiftLeft(esize, a, amount), + VectorLogicalShiftRight(esize, a, static_cast(esize - amount))); +} + +U128 IREmitter::VectorRotateRight(size_t esize, const U128& a, u8 amount) { + ASSERT(amount < esize); + + if (amount == 0) { + return a; + } + + return VectorOr(VectorLogicalShiftRight(esize, a, amount), + VectorLogicalShiftLeft(esize, a, static_cast(esize - amount))); +} + +U128 IREmitter::VectorRotateWholeVectorRight(const U128& a, u8 amount) { + ASSERT(amount % 32 == 0); + return Inst(Opcode::VectorRotateWholeVectorRight, a, Imm8(amount)); +} + +U128 IREmitter::VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorRoundingHalvingAddS8, a, b); + case 16: + return Inst(Opcode::VectorRoundingHalvingAddS16, a, b); + case 32: + return Inst(Opcode::VectorRoundingHalvingAddS32, a, b); + } + + UNREACHABLE(); +} + +U128 IREmitter::VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorRoundingHalvingAddU8, a, b); + case 16: + return Inst(Opcode::VectorRoundingHalvingAddU16, a, b); + case 32: + return Inst(Opcode::VectorRoundingHalvingAddU32, a, b); + } + + UNREACHABLE(); +} + +U128 IREmitter::VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorRoundingShiftLeftS8, a, b); + case 16: + return Inst(Opcode::VectorRoundingShiftLeftS16, a, b); + case 32: + return Inst(Opcode::VectorRoundingShiftLeftS32, a, b); + case 64: + return Inst(Opcode::VectorRoundingShiftLeftS64, a, b); + } + + UNREACHABLE(); +} + +U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorRoundingShiftLeftU8, a, b); + case 16: + return Inst(Opcode::VectorRoundingShiftLeftU16, a, b); + case 32: + return Inst(Opcode::VectorRoundingShiftLeftU32, a, b); + case 64: + return Inst(Opcode::VectorRoundingShiftLeftU64, a, b); + } + + UNREACHABLE(); +} + +U128 IREmitter::VectorSignExtend(size_t original_esize, const U128& a) { + switch (original_esize) { + case 8: + return Inst(Opcode::VectorSignExtend8, a); + case 16: + return Inst(Opcode::VectorSignExtend16, a); + case 32: + return Inst(Opcode::VectorSignExtend32, a); + case 64: + return Inst(Opcode::VectorSignExtend64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedAbsoluteDifference8, a, b); + case 16: + return Inst(Opcode::VectorSignedAbsoluteDifference16, a, b); + case 32: + return Inst(Opcode::VectorSignedAbsoluteDifference32, a, b); + } + UNREACHABLE(); +} + +UpperAndLower IREmitter::VectorSignedMultiply(size_t esize, const U128& a, const U128& b) { + const Value multiply = [&] { + switch (esize) { + case 16: + return Inst(Opcode::VectorSignedMultiply16, a, b); + case 32: + return Inst(Opcode::VectorSignedMultiply32, a, b); + } + UNREACHABLE(); + }(); + + return { + Inst(Opcode::GetUpperFromOp, multiply), + Inst(Opcode::GetLowerFromOp, multiply), + }; +} + +U128 IREmitter::VectorSignedSaturatedAbs(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedAbs8, a); + case 16: + return Inst(Opcode::VectorSignedSaturatedAbs16, a); + case 32: + return Inst(Opcode::VectorSignedSaturatedAbs32, a); + case 64: + return Inst(Opcode::VectorSignedSaturatedAbs64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned8, a, b); + case 16: + return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned32, a, b); + case 64: + return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedDoublingMultiplyHigh(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 16: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHigh16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHigh32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorSignedSaturatedDoublingMultiplyHighRounding(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 16: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding32, a, b); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::VectorSignedSaturatedDoublingMultiplyLong(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 16: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyLong16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyLong32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a) { + switch (original_esize) { + case 16: + return Inst(Opcode::VectorSignedSaturatedNarrowToSigned16, a); + case 32: + return Inst(Opcode::VectorSignedSaturatedNarrowToSigned32, a); + case 64: + return Inst(Opcode::VectorSignedSaturatedNarrowToSigned64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a) { + switch (original_esize) { + case 16: + return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned16, a); + case 32: + return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned32, a); + case 64: + return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedNeg(size_t esize, const U128& a) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedNeg8, a); + case 16: + return Inst(Opcode::VectorSignedSaturatedNeg16, a); + case 32: + return Inst(Opcode::VectorSignedSaturatedNeg32, a); + case 64: + return Inst(Opcode::VectorSignedSaturatedNeg64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedShiftLeft8, a, b); + case 16: + return Inst(Opcode::VectorSignedSaturatedShiftLeft16, a, b); + case 32: + return Inst(Opcode::VectorSignedSaturatedShiftLeft32, a, b); + case 64: + return Inst(Opcode::VectorSignedSaturatedShiftLeft64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount) { + ASSERT(shift_amount < esize); + switch (esize) { + case 8: + return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned8, a, Imm8(shift_amount)); + case 16: + return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned16, a, Imm8(shift_amount)); + case 32: + return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned32, a, Imm8(shift_amount)); + case 64: + return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned64, a, Imm8(shift_amount)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorSub(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSub8, a, b); + case 16: + return Inst(Opcode::VectorSub16, a, b); + case 32: + return Inst(Opcode::VectorSub32, a, b); + case 64: + return Inst(Opcode::VectorSub64, a, b); + } + UNREACHABLE(); +} + +Table IREmitter::VectorTable(std::vector values) { + ASSERT(values.size() >= 1 && values.size() <= 4); + values.resize(4); + return Inst(Opcode::VectorTable, values[0], values[1], values[2], values[3]); +} + +Table IREmitter::VectorTable(std::vector values) { + ASSERT(values.size() >= 1 && values.size() <= 4); + values.resize(4); + return Inst
(Opcode::VectorTable, values[0], values[1], values[2], values[3]); +} + +U64 IREmitter::VectorTableLookup(const U64& defaults, const Table& table, const U64& indices) { + ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U64); + return Inst(Opcode::VectorTableLookup64, defaults, table, indices); +} + +U128 IREmitter::VectorTableLookup(const U128& defaults, const Table& table, const U128& indices) { + ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U128); + return Inst(Opcode::VectorTableLookup128, defaults, table, indices); +} + +U128 IREmitter::VectorTranspose(size_t esize, const U128& a, const U128& b, bool part) { + switch (esize) { + case 8: + return Inst(Opcode::VectorTranspose8, a, b, Imm1(part)); + case 16: + return Inst(Opcode::VectorTranspose16, a, b, Imm1(part)); + case 32: + return Inst(Opcode::VectorTranspose32, a, b, Imm1(part)); + case 64: + return Inst(Opcode::VectorTranspose64, a, b, Imm1(part)); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorUnsignedAbsoluteDifference8, a, b); + case 16: + return Inst(Opcode::VectorUnsignedAbsoluteDifference16, a, b); + case 32: + return Inst(Opcode::VectorUnsignedAbsoluteDifference32, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorUnsignedRecipEstimate(const U128& a) { + return Inst(Opcode::VectorUnsignedRecipEstimate, a); +} + +U128 IREmitter::VectorUnsignedRecipSqrtEstimate(const U128& a) { + return Inst(Opcode::VectorUnsignedRecipSqrtEstimate, a); +} + +U128 IREmitter::VectorUnsignedSaturatedAccumulateSigned(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned8, a, b); + case 16: + return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned16, a, b); + case 32: + return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned32, a, b); + case 64: + return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) { + switch (esize) { + case 16: + return Inst(Opcode::VectorUnsignedSaturatedNarrow16, a); + case 32: + return Inst(Opcode::VectorUnsignedSaturatedNarrow32, a); + case 64: + return Inst(Opcode::VectorUnsignedSaturatedNarrow64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorUnsignedSaturatedShiftLeft8, a, b); + case 16: + return Inst(Opcode::VectorUnsignedSaturatedShiftLeft16, a, b); + case 32: + return Inst(Opcode::VectorUnsignedSaturatedShiftLeft32, a, b); + case 64: + return Inst(Opcode::VectorUnsignedSaturatedShiftLeft64, a, b); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) { + switch (original_esize) { + case 8: + return Inst(Opcode::VectorZeroExtend8, a); + case 16: + return Inst(Opcode::VectorZeroExtend16, a); + case 32: + return Inst(Opcode::VectorZeroExtend32, a); + case 64: + return Inst(Opcode::VectorZeroExtend64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::VectorZeroUpper(const U128& a) { + return Inst(Opcode::VectorZeroUpper, a); +} + +U128 IREmitter::ZeroVector() { + return Inst(Opcode::ZeroVector); +} + +U16U32U64 IREmitter::FPAbs(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPAbs16, a); + case Type::U32: + return Inst(Opcode::FPAbs32, a); + case Type::U64: + return Inst(Opcode::FPAbs64, a); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPAdd(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPAdd32, a, b); + case Type::U64: + return Inst(Opcode::FPAdd64, a, b); + default: + UNREACHABLE(); + } +} + +NZCV IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan) { + ASSERT(a.GetType() == b.GetType()); + + const IR::U1 exc_on_qnan_imm = Imm1(exc_on_qnan); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPCompare32, a, b, exc_on_qnan_imm); + case Type::U64: + return Inst(Opcode::FPCompare64, a, b, exc_on_qnan_imm); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPDiv(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPDiv32, a, b); + case Type::U64: + return Inst(Opcode::FPDiv64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMax(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMax32, a, b); + case Type::U64: + return Inst(Opcode::FPMax64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMaxNumeric(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMaxNumeric32, a, b); + case Type::U64: + return Inst(Opcode::FPMaxNumeric64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMin(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMin32, a, b); + case Type::U64: + return Inst(Opcode::FPMin64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMinNumeric(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMinNumeric32, a, b); + case Type::U64: + return Inst(Opcode::FPMinNumeric64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMul(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMul32, a, b); + case Type::U64: + return Inst(Opcode::FPMul64, a, b); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPMulAdd16, a, b, c); + case Type::U32: + return Inst(Opcode::FPMulAdd32, a, b, c); + case Type::U64: + return Inst(Opcode::FPMulAdd64, a, b, c); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPMulSub(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPMulSub16, a, b, c); + case Type::U32: + return Inst(Opcode::FPMulSub32, a, b, c); + case Type::U64: + return Inst(Opcode::FPMulSub64, a, b, c); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPMulX(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPMulX32, a, b); + case Type::U64: + return Inst(Opcode::FPMulX64, a, b); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPNeg(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPNeg16, a); + case Type::U32: + return Inst(Opcode::FPNeg32, a); + case Type::U64: + return Inst(Opcode::FPNeg64, a); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRecipEstimate(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRecipEstimate16, a); + case Type::U32: + return Inst(Opcode::FPRecipEstimate32, a); + case Type::U64: + return Inst(Opcode::FPRecipEstimate64, a); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRecipExponent16, a); + case Type::U32: + return Inst(Opcode::FPRecipExponent32, a); + case Type::U64: + return Inst(Opcode::FPRecipExponent64, a); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRecipStepFused16, a, b); + case Type::U32: + return Inst(Opcode::FPRecipStepFused32, a, b); + case Type::U64: + return Inst(Opcode::FPRecipStepFused64, a, b); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact) { + const u8 rounding_value = static_cast(rounding); + const IR::U1 exact_imm = Imm1(exact); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRoundInt16, a, rounding_value, exact_imm); + case Type::U32: + return Inst(Opcode::FPRoundInt32, a, rounding_value, exact_imm); + case Type::U64: + return Inst(Opcode::FPRoundInt64, a, rounding_value, exact_imm); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRSqrtEstimate(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRSqrtEstimate16, a); + case Type::U32: + return Inst(Opcode::FPRSqrtEstimate32, a); + case Type::U64: + return Inst(Opcode::FPRSqrtEstimate64, a); + default: + UNREACHABLE(); + } +} + +U16U32U64 IREmitter::FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRSqrtStepFused16, a, b); + case Type::U32: + return Inst(Opcode::FPRSqrtStepFused32, a, b); + case Type::U64: + return Inst(Opcode::FPRSqrtStepFused64, a, b); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPSqrt(const U32U64& a) { + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPSqrt32, a); + case Type::U64: + return Inst(Opcode::FPSqrt64, a); + default: + UNREACHABLE(); + } +} + +U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b) { + ASSERT(a.GetType() == b.GetType()); + + switch (a.GetType()) { + case Type::U32: + return Inst(Opcode::FPSub32, a, b); + case Type::U64: + return Inst(Opcode::FPSub64, a, b); + default: + UNREACHABLE(); + } +} + +U16 IREmitter::FPDoubleToHalf(const U64& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPDoubleToHalf, a, Imm8(static_cast(rounding))); +} + +U32 IREmitter::FPDoubleToSingle(const U64& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPDoubleToSingle, a, Imm8(static_cast(rounding))); +} + +U64 IREmitter::FPHalfToDouble(const U16& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPHalfToDouble, a, Imm8(static_cast(rounding))); +} + +U32 IREmitter::FPHalfToSingle(const U16& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPHalfToSingle, a, Imm8(static_cast(rounding))); +} + +U64 IREmitter::FPSingleToDouble(const U32& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPSingleToDouble, a, Imm8(static_cast(rounding))); +} + +U16 IREmitter::FPSingleToHalf(const U32& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPSingleToHalf, a, Imm8(static_cast(rounding))); +} + +U16 IREmitter::FPToFixedS16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 16); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedS16, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedS16, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedS16, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 32); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedS32, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedS32, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedS32, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U64 IREmitter::FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 64); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedS64, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedS64, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedS64, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U16 IREmitter::FPToFixedU16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 16); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedU16, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedU16, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedU16, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 32); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedU32, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedU32, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedU32, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U64 IREmitter::FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= 64); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPHalfToFixedU64, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPSingleToFixedU64, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPDoubleToFixedU64, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::FPSignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + + const IR::U8 fbits_imm = Imm8(static_cast(fbits)); + const IR::U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPFixedS16ToSingle, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPFixedS32ToSingle, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPFixedS64ToSingle, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U32 IREmitter::FPUnsignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + + const IR::U8 fbits_imm = Imm8(static_cast(fbits)); + const IR::U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPFixedU16ToSingle, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPFixedU32ToSingle, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPFixedU64ToSingle, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U64 IREmitter::FPSignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + + const IR::U8 fbits_imm = Imm8(static_cast(fbits)); + const IR::U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPFixedS16ToDouble, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPFixedS32ToDouble, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPFixedS64ToDouble, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U64 IREmitter::FPUnsignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { + ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); + + const IR::U8 fbits_imm = Imm8(static_cast(fbits)); + const IR::U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPFixedU16ToDouble, a, fbits_imm, rounding_imm); + case Type::U32: + return Inst(Opcode::FPFixedU32ToDouble, a, fbits_imm, rounding_imm); + case Type::U64: + return Inst(Opcode::FPFixedU64ToDouble, a, fbits_imm, rounding_imm); + default: + UNREACHABLE(); + } +} + +U128 IREmitter::FPVectorAbs(size_t esize, const U128& a) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorAbs16, a); + case 32: + return Inst(Opcode::FPVectorAbs32, a); + case 64: + return Inst(Opcode::FPVectorAbs64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorAdd32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorAdd64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorDiv32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorDiv64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorEqual16, a, b, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorEqual32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorEqual64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(esize == 32); + return Inst(Opcode::FPVectorFromHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); +} + +U128 IREmitter::FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(fbits <= esize); + switch (esize) { + case 32: + return Inst(Opcode::FPVectorFromSignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(fbits <= esize); + switch (esize) { + case 32: + return Inst(Opcode::FPVectorFromUnsignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorGreater(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorGreater32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorGreater64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorGreaterEqual32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorGreaterEqual64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMax(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMax32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMax64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMaxNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMaxNumeric32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMaxNumeric64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMin(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMin32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMin64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMinNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMinNumeric32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMinNumeric64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMul32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMul64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorMulAdd16, a, b, c, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorMulAdd32, a, b, c, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMulAdd64, a, b, c, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorMulX(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorMulX32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorMulX64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorNeg(size_t esize, const U128& a) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorNeg16, a); + case 32: + return Inst(Opcode::FPVectorNeg32, a); + case 64: + return Inst(Opcode::FPVectorNeg64, a); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorPairedAdd32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorPairedAdd64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorPairedAddLower32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorPairedAddLower64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorRecipEstimate16, a, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorRecipEstimate32, a, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorRecipStepFused16, a, b, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorRecipStepFused32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorRecipStepFused64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact, bool fpcr_controlled) { + const IR::U8 rounding_imm = Imm8(static_cast(rounding)); + const IR::U1 exact_imm = Imm1(exact); + + switch (esize) { + case 16: + return Inst(Opcode::FPVectorRoundInt16, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorRoundInt32, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorRoundInt64, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorRSqrtEstimate16, a, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorRSqrtEstimate32, a, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 16: + return Inst(Opcode::FPVectorRSqrtStepFused16, a, b, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorRSqrtStepFused32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorRSqrtStepFused64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorSqrt32, a, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorSqrt64, a, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorSub32, a, b, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled)); + } + UNREACHABLE(); +} + +U128 IREmitter::FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(esize == 32); + return Inst(Opcode::FPVectorToHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); +} + +U128 IREmitter::FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(fbits <= esize); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (esize) { + case 16: + return Inst(Opcode::FPVectorToSignedFixed16, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorToSignedFixed32, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorToSignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + } + + UNREACHABLE(); +} + +U128 IREmitter::FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled) { + ASSERT(fbits <= esize); + + const U8 fbits_imm = Imm8(static_cast(fbits)); + const U8 rounding_imm = Imm8(static_cast(rounding)); + + switch (esize) { + case 16: + return Inst(Opcode::FPVectorToUnsignedFixed16, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + case 32: + return Inst(Opcode::FPVectorToUnsignedFixed32, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + case 64: + return Inst(Opcode::FPVectorToUnsignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); + } + + UNREACHABLE(); +} + +void IREmitter::Breakpoint() { + Inst(Opcode::Breakpoint); +} + +void IREmitter::CallHostFunction(void (*fn)(void)) { + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), Value{}, Value{}, Value{}); +} + +void IREmitter::CallHostFunction(void (*fn)(u64), const U64& arg1) { + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, Value{}, Value{}); +} + +void IREmitter::CallHostFunction(void (*fn)(u64, u64), const U64& arg1, const U64& arg2) { + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2, Value{}); +} + +void IREmitter::CallHostFunction(void (*fn)(u64, u64, u64), const U64& arg1, const U64& arg2, const U64& arg3) { + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2, arg3); +} + +void IREmitter::SetTerm(const Terminal& terminal) { + block.SetTerminal(terminal); +} } // namespace Dynarmic::IR diff --git a/externals/dynarmic/src/dynarmic/ir/ir_emitter.h b/externals/dynarmic/src/dynarmic/ir/ir_emitter.h index dba34bcc56..d37df24572 100644 --- a/externals/dynarmic/src/dynarmic/ir/ir_emitter.h +++ b/externals/dynarmic/src/dynarmic/ir/ir_emitter.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,13 +5,8 @@ #pragma once -#include +#include -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/assert.h" -#include - -#include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/acc_type.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/location_descriptor.h" @@ -77,2878 +69,337 @@ public: Block& block; - U1 Imm1(bool imm1) const { - return U1(Value(imm1)); - } - - U8 Imm8(u8 imm8) const { - return U8(Value(imm8)); - } - - U16 Imm16(u16 imm16) const { - return U16(Value(imm16)); - } - - U32 Imm32(u32 imm32) const { - return U32(Value(imm32)); - } - - U64 Imm64(u64 imm64) const { - return U64(Value(imm64)); - } - - void PushRSB(const LocationDescriptor& return_location) { - Inst(Opcode::PushRSB, IR::Value(return_location.Value())); - } - - U64 Pack2x32To1x64(const U32& lo, const U32& hi) { - return Inst(Opcode::Pack2x32To1x64, lo, hi); - } - - U128 Pack2x64To1x128(const U64& lo, const U64& hi) { - return Inst(Opcode::Pack2x64To1x128, lo, hi); - } - - UAny LeastSignificant(size_t bitsize, const U32U64& value) { - switch (bitsize) { - case 8: - return LeastSignificantByte(value); - case 16: - return LeastSignificantHalf(value); - case 32: - if (value.GetType() == Type::U32) { - return value; - } - return LeastSignificantWord(value); - case 64: - ASSERT(value.GetType() == Type::U64); - return value; - } - ASSERT_FALSE("Invalid bitsize"); - } - - U32 LeastSignificantWord(const U64& value) { - return Inst(Opcode::LeastSignificantWord, value); - } - - U16 LeastSignificantHalf(U32U64 value) { - if (value.GetType() == Type::U64) { - value = LeastSignificantWord(value); - } - return Inst(Opcode::LeastSignificantHalf, value); - } - - U8 LeastSignificantByte(U32U64 value) { - if (value.GetType() == Type::U64) { - value = LeastSignificantWord(value); - } - return Inst(Opcode::LeastSignificantByte, value); - } - - ResultAndCarry MostSignificantWord(const U64& value) { - const auto result = Inst(Opcode::MostSignificantWord, value); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - U1 MostSignificantBit(const U32& value) { - return Inst(Opcode::MostSignificantBit, value); - } - - U1 IsZero(const U32& value) { - return Inst(Opcode::IsZero32, value); - } - - U1 IsZero(const U64& value) { - return Inst(Opcode::IsZero64, value); - } - - U1 IsZero(const U32U64& value) { - if (value.GetType() == Type::U32) { - return Inst(Opcode::IsZero32, value); - } else { - return Inst(Opcode::IsZero64, value); - } - } - - U1 TestBit(const U32U64& value, const U8& bit) { - if (value.GetType() == Type::U32) { - return Inst(Opcode::TestBit, IndeterminateExtendToLong(value), bit); - } else { - return Inst(Opcode::TestBit, value, bit); - } - } - - U32 ConditionalSelect(Cond cond, const U32& a, const U32& b) { - return Inst(Opcode::ConditionalSelect32, Value{cond}, a, b); - } - - U64 ConditionalSelect(Cond cond, const U64& a, const U64& b) { - return Inst(Opcode::ConditionalSelect64, Value{cond}, a, b); - } - - NZCV ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b) { - return Inst(Opcode::ConditionalSelectNZCV, Value{cond}, a, b); - } - - U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::ConditionalSelect32, Value{cond}, a, b); - } else { - return Inst(Opcode::ConditionalSelect64, Value{cond}, a, b); - } - } - - U1 GetCFlagFromNZCV(const NZCV& nzcv) { - return Inst(Opcode::GetCFlagFromNZCV, nzcv); - } - - NZCV NZCVFromPackedFlags(const U32& a) { - return Inst(Opcode::NZCVFromPackedFlags, a); - } - - NZCV NZCVFrom(const Value& value) { - return Inst(Opcode::GetNZCVFromOp, value); - } - - ResultAndCarry LogicalShiftLeft(const U32& value_in, const U8& shift_amount, const U1& carry_in) { - const auto result = Inst(Opcode::LogicalShiftLeft32, value_in, shift_amount, carry_in); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - ResultAndCarry LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { - const auto result = Inst(Opcode::LogicalShiftRight32, value_in, shift_amount, carry_in); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - ResultAndCarry ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { - const auto result = Inst(Opcode::ArithmeticShiftRight32, value_in, shift_amount, carry_in); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - ResultAndCarry RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) { - const auto result = Inst(Opcode::RotateRight32, value_in, shift_amount, carry_in); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - ResultAndCarry RotateRightExtended(const U32& value_in, const U1& carry_in) { - const auto result = Inst(Opcode::RotateRightExtended, value_in, carry_in); - const auto carry_out = Inst(Opcode::GetCarryFromOp, result); - return {result, carry_out}; - } - - U32U64 LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount) { - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::LogicalShiftLeft32, value_in, shift_amount, Imm1(0)); - } else { - return Inst(Opcode::LogicalShiftLeft64, value_in, shift_amount); - } - } - - U32U64 LogicalShiftRight(const U32U64& value_in, const U8& shift_amount) { - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::LogicalShiftRight32, value_in, shift_amount, Imm1(0)); - } else { - return Inst(Opcode::LogicalShiftRight64, value_in, shift_amount); - } - } - - U32U64 ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount) { - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::ArithmeticShiftRight32, value_in, shift_amount, Imm1(0)); - } else { - return Inst(Opcode::ArithmeticShiftRight64, value_in, shift_amount); - } - } - - U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount) { - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::RotateRight32, value_in, shift_amount, Imm1(0)); - } else { - return Inst(Opcode::RotateRight64, value_in, shift_amount); - } - } - - U32U64 LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::LogicalShiftLeftMasked32, value_in, shift_amount); - } else { - return Inst(Opcode::LogicalShiftLeftMasked64, value_in, shift_amount); - } - } - - U32U64 LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::LogicalShiftRightMasked32, value_in, shift_amount); - } else { - return Inst(Opcode::LogicalShiftRightMasked64, value_in, shift_amount); - } - } - - U32U64 ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::ArithmeticShiftRightMasked32, value_in, shift_amount); - } else { - return Inst(Opcode::ArithmeticShiftRightMasked64, value_in, shift_amount); - } - } - - U32U64 RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount) { - ASSERT(value_in.GetType() == shift_amount.GetType()); - if (value_in.GetType() == Type::U32) { - return Inst(Opcode::RotateRightMasked32, value_in, shift_amount); - } else { - return Inst(Opcode::RotateRightMasked64, value_in, shift_amount); - } - } - - U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Add32, a, b, carry_in); - } else { - return Inst(Opcode::Add64, a, b, carry_in); - } - } - - U32U64 Add(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Add32, a, b, Imm1(0)); - } else { - return Inst(Opcode::Add64, a, b, Imm1(0)); - } - } - - U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Sub32, a, b, carry_in); - } else { - return Inst(Opcode::Sub64, a, b, carry_in); - } - } - - U32U64 Sub(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Sub32, a, b, Imm1(1)); - } else { - return Inst(Opcode::Sub64, a, b, Imm1(1)); - } - } - - U32U64 Mul(const U32U64& a, const U32U64& b) { - if (a.GetType() == Type::U32) { - return Inst(Opcode::Mul32, a, b); - } - - return Inst(Opcode::Mul64, a, b); - } - - U64 UnsignedMultiplyHigh(const U64& a, const U64& b) { - return Inst(Opcode::UnsignedMultiplyHigh64, a, b); - } - - U64 SignedMultiplyHigh(const U64& a, const U64& b) { - return Inst(Opcode::SignedMultiplyHigh64, a, b); - } - - U32U64 UnsignedDiv(const U32U64& a, const U32U64& b) { - if (a.GetType() == Type::U32) { - return Inst(Opcode::UnsignedDiv32, a, b); - } - - return Inst(Opcode::UnsignedDiv64, a, b); - } - - U32U64 SignedDiv(const U32U64& a, const U32U64& b) { - if (a.GetType() == Type::U32) { - return Inst(Opcode::SignedDiv32, a, b); - } - - return Inst(Opcode::SignedDiv64, a, b); - } - - U32U64 And(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::And32, a, b); - } else { - return Inst(Opcode::And64, a, b); - } - } - - U32U64 AndNot(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::AndNot32, a, b); - } else { - return Inst(Opcode::AndNot64, a, b); - } - } - - U32U64 Eor(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Eor32, a, b); - } else { - return Inst(Opcode::Eor64, a, b); - } - } - - U32U64 Or(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - if (a.GetType() == Type::U32) { - return Inst(Opcode::Or32, a, b); - } else { - return Inst(Opcode::Or64, a, b); - } - } - - U32U64 Not(const U32U64& a) { - if (a.GetType() == Type::U32) { - return Inst(Opcode::Not32, a); - } else { - return Inst(Opcode::Not64, a); - } - } - - U64 SignExtendToLong(const UAny& a) { - switch (a.GetType()) { - case Type::U8: - return Inst(Opcode::SignExtendByteToLong, a); - case Type::U16: - return Inst(Opcode::SignExtendHalfToLong, a); - case Type::U32: - return Inst(Opcode::SignExtendWordToLong, a); - case Type::U64: - return U64(a); - default: - UNREACHABLE(); - } - } - - U32 SignExtendToWord(const UAny& a) { - switch (a.GetType()) { - case Type::U8: - return Inst(Opcode::SignExtendByteToWord, a); - case Type::U16: - return Inst(Opcode::SignExtendHalfToWord, a); - case Type::U32: - return U32(a); - case Type::U64: - return Inst(Opcode::LeastSignificantWord, a); - default: - UNREACHABLE(); - } - } - - U64 SignExtendWordToLong(const U32& a) { - return Inst(Opcode::SignExtendWordToLong, a); - } - - U32 SignExtendHalfToWord(const U16& a) { - return Inst(Opcode::SignExtendHalfToWord, a); - } - - U32 SignExtendByteToWord(const U8& a) { - return Inst(Opcode::SignExtendByteToWord, a); - } - - U64 ZeroExtendToLong(const UAny& a) { - switch (a.GetType()) { - case Type::U8: - return Inst(Opcode::ZeroExtendByteToLong, a); - case Type::U16: - return Inst(Opcode::ZeroExtendHalfToLong, a); - case Type::U32: - return Inst(Opcode::ZeroExtendWordToLong, a); - case Type::U64: - return U64(a); - default: - UNREACHABLE(); - } - } - - U32 ZeroExtendToWord(const UAny& a) { - switch (a.GetType()) { - case Type::U8: - return Inst(Opcode::ZeroExtendByteToWord, a); - case Type::U16: - return Inst(Opcode::ZeroExtendHalfToWord, a); - case Type::U32: - return U32(a); - case Type::U64: - return Inst(Opcode::LeastSignificantWord, a); - default: - UNREACHABLE(); - } - } - - U128 ZeroExtendToQuad(const UAny& a) { - return Inst(Opcode::ZeroExtendLongToQuad, ZeroExtendToLong(a)); - } - - U64 ZeroExtendWordToLong(const U32& a) { - return Inst(Opcode::ZeroExtendWordToLong, a); - } - - U32 ZeroExtendHalfToWord(const U16& a) { - return Inst(Opcode::ZeroExtendHalfToWord, a); - } - - U32 ZeroExtendByteToWord(const U8& a) { - return Inst(Opcode::ZeroExtendByteToWord, a); - } - - U32 IndeterminateExtendToWord(const UAny& a) { - // TODO: Implement properly - return ZeroExtendToWord(a); - } - - U64 IndeterminateExtendToLong(const UAny& a) { - // TODO: Implement properly - return ZeroExtendToLong(a); - } - - U32 ByteReverseWord(const U32& a) { - return Inst(Opcode::ByteReverseWord, a); - } - - U16 ByteReverseHalf(const U16& a) { - return Inst(Opcode::ByteReverseHalf, a); - } - - U64 ByteReverseDual(const U64& a) { - return Inst(Opcode::ByteReverseDual, a); - } - - U32U64 CountLeadingZeros(const U32U64& a) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::CountLeadingZeros32, a); - } - - return Inst(Opcode::CountLeadingZeros64, a); - } - - U32U64 ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::ExtractRegister32, a, b, lsb); - } - - return Inst(Opcode::ExtractRegister64, a, b, lsb); - } - - U32U64 ReplicateBit(const U32U64& a, u8 bit) { - if (a.GetType() == IR::Type::U32) { - ASSERT(bit < 32); - return Inst(Opcode::ReplicateBit32, a, Imm8(bit)); - } - - ASSERT(bit < 64); - return Inst(Opcode::ReplicateBit64, a, Imm8(bit)); - } - - U32U64 MaxSigned(const U32U64& a, const U32U64& b) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::MaxSigned32, a, b); - } - - return Inst(Opcode::MaxSigned64, a, b); - } - - U32U64 MaxUnsigned(const U32U64& a, const U32U64& b) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::MaxUnsigned32, a, b); - } - - return Inst(Opcode::MaxUnsigned64, a, b); - } - - U32U64 MinSigned(const U32U64& a, const U32U64& b) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::MinSigned32, a, b); - } - - return Inst(Opcode::MinSigned64, a, b); - } - - U32U64 MinUnsigned(const U32U64& a, const U32U64& b) { - if (a.GetType() == IR::Type::U32) { - return Inst(Opcode::MinUnsigned32, a, b); - } - - return Inst(Opcode::MinUnsigned64, a, b); - } - - ResultAndOverflow SignedSaturatedAddWithFlag(const U32& a, const U32& b) { - const auto result = Inst(Opcode::SignedSaturatedAddWithFlag32, a, b); - const auto overflow = Inst(Opcode::GetOverflowFromOp, result); - return {result, overflow}; - } - - ResultAndOverflow SignedSaturatedSubWithFlag(const U32& a, const U32& b) { - const auto result = Inst(Opcode::SignedSaturatedSubWithFlag32, a, b); - const auto overflow = Inst(Opcode::GetOverflowFromOp, result); - return {result, overflow}; - } - - ResultAndOverflow SignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { - ASSERT(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32); - const auto result = Inst(Opcode::SignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); - const auto overflow = Inst(Opcode::GetOverflowFromOp, result); - return {result, overflow}; - } - - ResultAndOverflow UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to) { - ASSERT(bit_size_to_saturate_to <= 31); - const auto result = Inst(Opcode::UnsignedSaturation, a, Imm8(static_cast(bit_size_to_saturate_to))); - const auto overflow = Inst(Opcode::GetOverflowFromOp, result); - return {result, overflow}; - } - - UAny SignedSaturatedAdd(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); - const auto result = [&]() -> IR::UAny { - switch (a.GetType()) { - case IR::Type::U8: - return Inst(Opcode::SignedSaturatedAdd8, a, b); - case IR::Type::U16: - return Inst(Opcode::SignedSaturatedAdd16, a, b); - case IR::Type::U32: - return Inst(Opcode::SignedSaturatedAdd32, a, b); - case IR::Type::U64: - return Inst(Opcode::SignedSaturatedAdd64, a, b); - default: - return IR::UAny{}; - } - }(); - return result; - } - - UAny SignedSaturatedDoublingMultiplyReturnHigh(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); - const auto result = [&]() -> IR::UAny { - switch (a.GetType()) { - case IR::Type::U16: - return Inst(Opcode::SignedSaturatedDoublingMultiplyReturnHigh16, a, b); - case IR::Type::U32: - return Inst(Opcode::SignedSaturatedDoublingMultiplyReturnHigh32, a, b); - default: - UNREACHABLE(); - } - }(); - return result; - } - - UAny SignedSaturatedSub(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); - const auto result = [&]() -> IR::UAny { - switch (a.GetType()) { - case IR::Type::U8: - return Inst(Opcode::SignedSaturatedSub8, a, b); - case IR::Type::U16: - return Inst(Opcode::SignedSaturatedSub16, a, b); - case IR::Type::U32: - return Inst(Opcode::SignedSaturatedSub32, a, b); - case IR::Type::U64: - return Inst(Opcode::SignedSaturatedSub64, a, b); - default: - return IR::UAny{}; - } - }(); - return result; - } - - UAny UnsignedSaturatedAdd(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); - const auto result = [&]() -> IR::UAny { - switch (a.GetType()) { - case IR::Type::U8: - return Inst(Opcode::UnsignedSaturatedAdd8, a, b); - case IR::Type::U16: - return Inst(Opcode::UnsignedSaturatedAdd16, a, b); - case IR::Type::U32: - return Inst(Opcode::UnsignedSaturatedAdd32, a, b); - case IR::Type::U64: - return Inst(Opcode::UnsignedSaturatedAdd64, a, b); - default: - return IR::UAny{}; - } - }(); - return result; - } - - UAny UnsignedSaturatedSub(const UAny& a, const UAny& b) { - ASSERT(a.GetType() == b.GetType()); - const auto result = [&]() -> IR::UAny { - switch (a.GetType()) { - case IR::Type::U8: - return Inst(Opcode::UnsignedSaturatedSub8, a, b); - case IR::Type::U16: - return Inst(Opcode::UnsignedSaturatedSub16, a, b); - case IR::Type::U32: - return Inst(Opcode::UnsignedSaturatedSub32, a, b); - case IR::Type::U64: - return Inst(Opcode::UnsignedSaturatedSub64, a, b); - default: - return IR::UAny{}; - } - }(); - return result; - } - - U128 VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedAdd8, a, b); - case 16: - return Inst(Opcode::VectorSignedSaturatedAdd16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedAdd32, a, b); - case 64: - return Inst(Opcode::VectorSignedSaturatedAdd64, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedSub8, a, b); - case 16: - return Inst(Opcode::VectorSignedSaturatedSub16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedSub32, a, b); - case 64: - return Inst(Opcode::VectorSignedSaturatedSub64, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorUnsignedSaturatedAdd8, a, b); - case 16: - return Inst(Opcode::VectorUnsignedSaturatedAdd16, a, b); - case 32: - return Inst(Opcode::VectorUnsignedSaturatedAdd32, a, b); - case 64: - return Inst(Opcode::VectorUnsignedSaturatedAdd64, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorUnsignedSaturatedSub8, a, b); - case 16: - return Inst(Opcode::VectorUnsignedSaturatedSub16, a, b); - case 32: - return Inst(Opcode::VectorUnsignedSaturatedSub32, a, b); - case 64: - return Inst(Opcode::VectorUnsignedSaturatedSub64, a, b); - default: - UNREACHABLE(); - } - } - - ResultAndGE PackedAddU8(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddU8, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedAddS8(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddS8, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedAddU16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddU16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedAddS16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddS16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubU8(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubU8, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubS8(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubS8, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubU16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubU16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubS16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubS16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedAddSubU16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddSubU16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedAddSubS16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedAddSubS16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubAddU16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubAddU16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - ResultAndGE PackedSubAddS16(const U32& a, const U32& b) { - const auto result = Inst(Opcode::PackedSubAddS16, a, b); - const auto ge = Inst(Opcode::GetGEFromOp, result); - return {result, ge}; - } - - U32 PackedHalvingAddU8(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddU8, a, b); - } - - U32 PackedHalvingAddS8(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddS8, a, b); - } - - U32 PackedHalvingSubU8(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubU8, a, b); - } - - U32 PackedHalvingSubS8(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubS8, a, b); - } - - U32 PackedHalvingAddU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddU16, a, b); - } - - U32 PackedHalvingAddS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddS16, a, b); - } - - U32 PackedHalvingSubU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubU16, a, b); - } - - U32 PackedHalvingSubS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubS16, a, b); - } - - U32 PackedHalvingAddSubU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddSubU16, a, b); - } - - U32 PackedHalvingAddSubS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingAddSubS16, a, b); - } - - U32 PackedHalvingSubAddU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubAddU16, a, b); - } - - U32 PackedHalvingSubAddS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedHalvingSubAddS16, a, b); - } - - U32 PackedSaturatedAddU8(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedAddU8, a, b); - } - - U32 PackedSaturatedAddS8(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedAddS8, a, b); - } - - U32 PackedSaturatedSubU8(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedSubU8, a, b); - } - - U32 PackedSaturatedSubS8(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedSubS8, a, b); - } - - U32 PackedSaturatedAddU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedAddU16, a, b); - } - - U32 PackedSaturatedAddS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedAddS16, a, b); - } - - U32 PackedSaturatedSubU16(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedSubU16, a, b); - } - - U32 PackedSaturatedSubS16(const U32& a, const U32& b) { - return Inst(Opcode::PackedSaturatedSubS16, a, b); - } - - U32 PackedAbsDiffSumU8(const U32& a, const U32& b) { - return Inst(Opcode::PackedAbsDiffSumU8, a, b); - } - - U32 PackedSelect(const U32& ge, const U32& a, const U32& b) { - return Inst(Opcode::PackedSelect, ge, a, b); - } - - U32 CRC32Castagnoli8(const U32& a, const U32& b) { - return Inst(Opcode::CRC32Castagnoli8, a, b); - } - - U32 CRC32Castagnoli16(const U32& a, const U32& b) { - return Inst(Opcode::CRC32Castagnoli16, a, b); - } - - U32 CRC32Castagnoli32(const U32& a, const U32& b) { - return Inst(Opcode::CRC32Castagnoli32, a, b); - } - - U32 CRC32Castagnoli64(const U32& a, const U64& b) { - return Inst(Opcode::CRC32Castagnoli64, a, b); - } - - U32 CRC32ISO8(const U32& a, const U32& b) { - return Inst(Opcode::CRC32ISO8, a, b); - } - - U32 CRC32ISO16(const U32& a, const U32& b) { - return Inst(Opcode::CRC32ISO16, a, b); - } - - U32 CRC32ISO32(const U32& a, const U32& b) { - return Inst(Opcode::CRC32ISO32, a, b); - } - - U32 CRC32ISO64(const U32& a, const U64& b) { - return Inst(Opcode::CRC32ISO64, a, b); - } - - U128 AESDecryptSingleRound(const U128& a) { - return Inst(Opcode::AESDecryptSingleRound, a); - } - - U128 AESEncryptSingleRound(const U128& a) { - return Inst(Opcode::AESEncryptSingleRound, a); - } - - U128 AESInverseMixColumns(const U128& a) { - return Inst(Opcode::AESInverseMixColumns, a); - } - - U128 AESMixColumns(const U128& a) { - return Inst(Opcode::AESMixColumns, a); - } - - U8 SM4AccessSubstitutionBox(const U8& a) { - return Inst(Opcode::SM4AccessSubstitutionBox, a); - } - - U128 SHA256Hash(const U128& x, const U128& y, const U128& w, bool part1) { - return Inst(Opcode::SHA256Hash, x, y, w, Imm1(part1)); - } - - U128 SHA256MessageSchedule0(const U128& x, const U128& y) { - return Inst(Opcode::SHA256MessageSchedule0, x, y); - } - - U128 SHA256MessageSchedule1(const U128& x, const U128& y, const U128& z) { - return Inst(Opcode::SHA256MessageSchedule1, x, y, z); - } - - UAny VectorGetElement(size_t esize, const U128& a, size_t index) { - ASSERT_MSG(esize * index < 128, "Invalid index"); - switch (esize) { - case 8: - return Inst(Opcode::VectorGetElement8, a, Imm8(static_cast(index))); - case 16: - return Inst(Opcode::VectorGetElement16, a, Imm8(static_cast(index))); - case 32: - return Inst(Opcode::VectorGetElement32, a, Imm8(static_cast(index))); - case 64: - return Inst(Opcode::VectorGetElement64, a, Imm8(static_cast(index))); - default: - UNREACHABLE(); - } - } - - U128 VectorSetElement(size_t esize, const U128& a, size_t index, const IR::UAny& elem) { - ASSERT_MSG(esize * index < 128, "Invalid index"); - switch (esize) { - case 8: - return Inst(Opcode::VectorSetElement8, a, Imm8(static_cast(index)), elem); - case 16: - return Inst(Opcode::VectorSetElement16, a, Imm8(static_cast(index)), elem); - case 32: - return Inst(Opcode::VectorSetElement32, a, Imm8(static_cast(index)), elem); - case 64: - return Inst(Opcode::VectorSetElement64, a, Imm8(static_cast(index)), elem); - default: - UNREACHABLE(); - } - } - - U128 VectorAbs(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorAbs8, a); - case 16: - return Inst(Opcode::VectorAbs16, a); - case 32: - return Inst(Opcode::VectorAbs32, a); - case 64: - return Inst(Opcode::VectorAbs64, a); - } - UNREACHABLE(); - } - - U128 VectorAdd(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorAdd8, a, b); - case 16: - return Inst(Opcode::VectorAdd16, a, b); - case 32: - return Inst(Opcode::VectorAdd32, a, b); - case 64: - return Inst(Opcode::VectorAdd64, a, b); - } - UNREACHABLE(); - } - - U128 VectorAnd(const U128& a, const U128& b) { - return Inst(Opcode::VectorAnd, a, b); - } - - U128 VectorAndNot(const U128& a, const U128& b) { - return Inst(Opcode::VectorAndNot, a, b); - } - - U128 VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount) { - switch (esize) { - case 8: - return Inst(Opcode::VectorArithmeticShiftRight8, a, Imm8(shift_amount)); - case 16: - return Inst(Opcode::VectorArithmeticShiftRight16, a, Imm8(shift_amount)); - case 32: - return Inst(Opcode::VectorArithmeticShiftRight32, a, Imm8(shift_amount)); - case 64: - return Inst(Opcode::VectorArithmeticShiftRight64, a, Imm8(shift_amount)); - } - UNREACHABLE(); - } - - U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorArithmeticVShift8, a, b); - case 16: - return Inst(Opcode::VectorArithmeticVShift16, a, b); - case 32: - return Inst(Opcode::VectorArithmeticVShift32, a, b); - case 64: - return Inst(Opcode::VectorArithmeticVShift64, a, b); - } - UNREACHABLE(); - } - - U128 VectorBroadcastLower(size_t esize, const UAny& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorBroadcastLower8, U8(a)); - case 16: - return Inst(Opcode::VectorBroadcastLower16, U16(a)); - case 32: - return Inst(Opcode::VectorBroadcastLower32, U32(a)); - } - UNREACHABLE(); - } - - U128 VectorBroadcast(size_t esize, const UAny& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorBroadcast8, U8(a)); - case 16: - return Inst(Opcode::VectorBroadcast16, U16(a)); - case 32: - return Inst(Opcode::VectorBroadcast32, U32(a)); - case 64: - return Inst(Opcode::VectorBroadcast64, U64(a)); - } - UNREACHABLE(); - } - - U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) { - ASSERT_MSG(esize * index < 128, "Invalid index"); - switch (esize) { - case 8: - return Inst(Opcode::VectorBroadcastElementLower8, a, u8(index)); - case 16: - return Inst(Opcode::VectorBroadcastElementLower16, a, u8(index)); - case 32: - return Inst(Opcode::VectorBroadcastElementLower32, a, u8(index)); - } - UNREACHABLE(); - } - - U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index) { - ASSERT_MSG(esize * index < 128, "Invalid index"); - switch (esize) { - case 8: - return Inst(Opcode::VectorBroadcastElement8, a, u8(index)); - case 16: - return Inst(Opcode::VectorBroadcastElement16, a, u8(index)); - case 32: - return Inst(Opcode::VectorBroadcastElement32, a, u8(index)); - case 64: - return Inst(Opcode::VectorBroadcastElement64, a, u8(index)); - } - UNREACHABLE(); - } - - U128 VectorCountLeadingZeros(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorCountLeadingZeros8, a); - case 16: - return Inst(Opcode::VectorCountLeadingZeros16, a); - case 32: - return Inst(Opcode::VectorCountLeadingZeros32, a); - } - UNREACHABLE(); - } - - U128 VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorDeinterleaveEven8, a, b); - case 16: - return Inst(Opcode::VectorDeinterleaveEven16, a, b); - case 32: - return Inst(Opcode::VectorDeinterleaveEven32, a, b); - case 64: - return Inst(Opcode::VectorDeinterleaveEven64, a, b); - } - UNREACHABLE(); - } - - U128 VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorDeinterleaveOdd8, a, b); - case 16: - return Inst(Opcode::VectorDeinterleaveOdd16, a, b); - case 32: - return Inst(Opcode::VectorDeinterleaveOdd32, a, b); - case 64: - return Inst(Opcode::VectorDeinterleaveOdd64, a, b); - } - UNREACHABLE(); - } - - U128 VectorDeinterleaveEvenLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorDeinterleaveEvenLower8, a, b); - case 16: - return Inst(Opcode::VectorDeinterleaveEvenLower16, a, b); - case 32: - return Inst(Opcode::VectorDeinterleaveEvenLower32, a, b); - } - UNREACHABLE(); - } - - U128 VectorDeinterleaveOddLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorDeinterleaveOddLower8, a, b); - case 16: - return Inst(Opcode::VectorDeinterleaveOddLower16, a, b); - case 32: - return Inst(Opcode::VectorDeinterleaveOddLower32, a, b); - } - UNREACHABLE(); - } - - U128 VectorEor(const U128& a, const U128& b) { - return Inst(Opcode::VectorEor, a, b); - } - - U128 VectorEqual(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorEqual8, a, b); - case 16: - return Inst(Opcode::VectorEqual16, a, b); - case 32: - return Inst(Opcode::VectorEqual32, a, b); - case 64: - return Inst(Opcode::VectorEqual64, a, b); - case 128: - return Inst(Opcode::VectorEqual128, a, b); - } - UNREACHABLE(); - } - - U128 VectorExtract(const U128& a, const U128& b, size_t position) { - ASSERT(position <= 128); - return Inst(Opcode::VectorExtract, a, b, Imm8(static_cast(position))); - } - - U128 VectorExtractLower(const U128& a, const U128& b, size_t position) { - ASSERT(position <= 64); - return Inst(Opcode::VectorExtractLower, a, b, Imm8(static_cast(position))); - } - - U128 VectorGreaterSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorGreaterS8, a, b); - case 16: - return Inst(Opcode::VectorGreaterS16, a, b); - case 32: - return Inst(Opcode::VectorGreaterS32, a, b); - case 64: - return Inst(Opcode::VectorGreaterS64, a, b); - } - UNREACHABLE(); - } - - U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b) { - return VectorOr(VectorGreaterSigned(esize, a, b), VectorEqual(esize, a, b)); - } - - U128 VectorGreaterEqualUnsigned(size_t esize, const U128& a, const U128& b) { - return VectorEqual(esize, VectorMaxUnsigned(esize, a, b), a); - } - - U128 VectorGreaterUnsigned(size_t esize, const U128& a, const U128& b) { - return VectorNot(VectorEqual(esize, VectorMinUnsigned(esize, a, b), a)); - } - - U128 VectorHalvingAddSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorHalvingAddS8, a, b); - case 16: - return Inst(Opcode::VectorHalvingAddS16, a, b); - case 32: - return Inst(Opcode::VectorHalvingAddS32, a, b); - } - UNREACHABLE(); - } - - U128 VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorHalvingAddU8, a, b); - case 16: - return Inst(Opcode::VectorHalvingAddU16, a, b); - case 32: - return Inst(Opcode::VectorHalvingAddU32, a, b); - } - UNREACHABLE(); - } - - U128 VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorHalvingSubS8, a, b); - case 16: - return Inst(Opcode::VectorHalvingSubS16, a, b); - case 32: - return Inst(Opcode::VectorHalvingSubS32, a, b); - } - UNREACHABLE(); - } - - U128 VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorHalvingSubU8, a, b); - case 16: - return Inst(Opcode::VectorHalvingSubU16, a, b); - case 32: - return Inst(Opcode::VectorHalvingSubU32, a, b); - } - UNREACHABLE(); - } - - U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorInterleaveLower8, a, b); - case 16: - return Inst(Opcode::VectorInterleaveLower16, a, b); - case 32: - return Inst(Opcode::VectorInterleaveLower32, a, b); - case 64: - return Inst(Opcode::VectorInterleaveLower64, a, b); - } - UNREACHABLE(); - } - - U128 VectorInterleaveUpper(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorInterleaveUpper8, a, b); - case 16: - return Inst(Opcode::VectorInterleaveUpper16, a, b); - case 32: - return Inst(Opcode::VectorInterleaveUpper32, a, b); - case 64: - return Inst(Opcode::VectorInterleaveUpper64, a, b); - } - UNREACHABLE(); - } - - U128 VectorLessEqualSigned(size_t esize, const U128& a, const U128& b) { - return VectorNot(VectorGreaterSigned(esize, a, b)); - } - - U128 VectorLessEqualUnsigned(size_t esize, const U128& a, const U128& b) { - return VectorEqual(esize, VectorMinUnsigned(esize, a, b), a); - } - - U128 VectorLessSigned(size_t esize, const U128& a, const U128& b) { - return VectorNot(VectorOr(VectorGreaterSigned(esize, a, b), VectorEqual(esize, a, b))); - } - - U128 VectorLessUnsigned(size_t esize, const U128& a, const U128& b) { - return VectorNot(VectorEqual(esize, VectorMaxUnsigned(esize, a, b), a)); - } - - U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount) { - switch (esize) { - case 8: - return Inst(Opcode::VectorLogicalShiftLeft8, a, Imm8(shift_amount)); - case 16: - return Inst(Opcode::VectorLogicalShiftLeft16, a, Imm8(shift_amount)); - case 32: - return Inst(Opcode::VectorLogicalShiftLeft32, a, Imm8(shift_amount)); - case 64: - return Inst(Opcode::VectorLogicalShiftLeft64, a, Imm8(shift_amount)); - } - UNREACHABLE(); - } - - U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) { - switch (esize) { - case 8: - return Inst(Opcode::VectorLogicalShiftRight8, a, Imm8(shift_amount)); - case 16: - return Inst(Opcode::VectorLogicalShiftRight16, a, Imm8(shift_amount)); - case 32: - return Inst(Opcode::VectorLogicalShiftRight32, a, Imm8(shift_amount)); - case 64: - return Inst(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount)); - } - UNREACHABLE(); - } - - U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorLogicalVShift8, a, b); - case 16: - return Inst(Opcode::VectorLogicalVShift16, a, b); - case 32: - return Inst(Opcode::VectorLogicalVShift32, a, b); - case 64: - return Inst(Opcode::VectorLogicalVShift64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMaxS8, a, b); - case 16: - return Inst(Opcode::VectorMaxS16, a, b); - case 32: - return Inst(Opcode::VectorMaxS32, a, b); - case 64: - return Inst(Opcode::VectorMaxS64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMaxU8, a, b); - case 16: - return Inst(Opcode::VectorMaxU16, a, b); - case 32: - return Inst(Opcode::VectorMaxU32, a, b); - case 64: - return Inst(Opcode::VectorMaxU64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMinSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMinS8, a, b); - case 16: - return Inst(Opcode::VectorMinS16, a, b); - case 32: - return Inst(Opcode::VectorMinS32, a, b); - case 64: - return Inst(Opcode::VectorMinS64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMinUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMinU8, a, b); - case 16: - return Inst(Opcode::VectorMinU16, a, b); - case 32: - return Inst(Opcode::VectorMinU32, a, b); - case 64: - return Inst(Opcode::VectorMinU64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMultiply(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMultiply8, a, b); - case 16: - return Inst(Opcode::VectorMultiply16, a, b); - case 32: - return Inst(Opcode::VectorMultiply32, a, b); - case 64: - return Inst(Opcode::VectorMultiply64, a, b); - } - UNREACHABLE(); - } - - U128 VectorMultiplySignedWiden(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMultiplySignedWiden8, a, b); - case 16: - return Inst(Opcode::VectorMultiplySignedWiden16, a, b); - case 32: - return Inst(Opcode::VectorMultiplySignedWiden32, a, b); - } - UNREACHABLE(); - } - - U128 VectorMultiplyUnsignedWiden(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorMultiplyUnsignedWiden8, a, b); - case 16: - return Inst(Opcode::VectorMultiplyUnsignedWiden16, a, b); - case 32: - return Inst(Opcode::VectorMultiplyUnsignedWiden32, a, b); - } - UNREACHABLE(); - } - - U128 VectorNarrow(size_t original_esize, const U128& a) { - switch (original_esize) { - case 16: - return Inst(Opcode::VectorNarrow16, a); - case 32: - return Inst(Opcode::VectorNarrow32, a); - case 64: - return Inst(Opcode::VectorNarrow64, a); - } - UNREACHABLE(); - } - - U128 VectorNot(const U128& a) { - return Inst(Opcode::VectorNot, a); - } - - U128 VectorOr(const U128& a, const U128& b) { - return Inst(Opcode::VectorOr, a, b); - } - - U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedAdd8, a, b); - case 16: - return Inst(Opcode::VectorPairedAdd16, a, b); - case 32: - return Inst(Opcode::VectorPairedAdd32, a, b); - case 64: - return Inst(Opcode::VectorPairedAdd64, a, b); - } - UNREACHABLE(); - } - - U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedAddLower8, a, b); - case 16: - return Inst(Opcode::VectorPairedAddLower16, a, b); - case 32: - return Inst(Opcode::VectorPairedAddLower32, a, b); - } - UNREACHABLE(); - } - - U128 VectorPairedAddSignedWiden(size_t original_esize, const U128& a) { - switch (original_esize) { - case 8: - return Inst(Opcode::VectorPairedAddSignedWiden8, a); - case 16: - return Inst(Opcode::VectorPairedAddSignedWiden16, a); - case 32: - return Inst(Opcode::VectorPairedAddSignedWiden32, a); - } - UNREACHABLE(); - } - - U128 VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a) { - switch (original_esize) { - case 8: - return Inst(Opcode::VectorPairedAddUnsignedWiden8, a); - case 16: - return Inst(Opcode::VectorPairedAddUnsignedWiden16, a); - case 32: - return Inst(Opcode::VectorPairedAddUnsignedWiden32, a); - } - UNREACHABLE(); - } - - U128 VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMaxS8, a, b); - case 16: - return Inst(Opcode::VectorPairedMaxS16, a, b); - case 32: - return Inst(Opcode::VectorPairedMaxS32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMaxUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMaxU8, a, b); - case 16: - return Inst(Opcode::VectorPairedMaxU16, a, b); - case 32: - return Inst(Opcode::VectorPairedMaxU32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMinSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMinS8, a, b); - case 16: - return Inst(Opcode::VectorPairedMinS16, a, b); - case 32: - return Inst(Opcode::VectorPairedMinS32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMinUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMinU8, a, b); - case 16: - return Inst(Opcode::VectorPairedMinU16, a, b); - case 32: - return Inst(Opcode::VectorPairedMinU32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMaxSignedLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMaxLowerS8, a, b); - case 16: - return Inst(Opcode::VectorPairedMaxLowerS16, a, b); - case 32: - return Inst(Opcode::VectorPairedMaxLowerS32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMaxUnsignedLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMaxLowerU8, a, b); - case 16: - return Inst(Opcode::VectorPairedMaxLowerU16, a, b); - case 32: - return Inst(Opcode::VectorPairedMaxLowerU32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMinSignedLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMinLowerS8, a, b); - case 16: - return Inst(Opcode::VectorPairedMinLowerS16, a, b); - case 32: - return Inst(Opcode::VectorPairedMinLowerS32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPairedMinUnsignedLower(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPairedMinLowerU8, a, b); - case 16: - return Inst(Opcode::VectorPairedMinLowerU16, a, b); - case 32: - return Inst(Opcode::VectorPairedMinLowerU32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPolynomialMultiply(const U128& a, const U128& b) { - return Inst(Opcode::VectorPolynomialMultiply8, a, b); - } - - U128 VectorPolynomialMultiplyLong(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorPolynomialMultiplyLong8, a, b); - case 64: - return Inst(Opcode::VectorPolynomialMultiplyLong64, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorPopulationCount(const U128& a) { - return Inst(Opcode::VectorPopulationCount, a); - } - - U128 VectorReverseBits(const U128& a) { - return Inst(Opcode::VectorReverseBits, a); - } - - U128 VectorReverseElementsInHalfGroups(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorReverseElementsInHalfGroups8, a); - default: - UNREACHABLE(); - } - } - - U128 VectorReverseElementsInWordGroups(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorReverseElementsInWordGroups8, a); - case 16: - return Inst(Opcode::VectorReverseElementsInWordGroups16, a); - default: - UNREACHABLE(); - } - } - - U128 VectorReverseElementsInLongGroups(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorReverseElementsInLongGroups8, a); - case 16: - return Inst(Opcode::VectorReverseElementsInLongGroups16, a); - case 32: - return Inst(Opcode::VectorReverseElementsInLongGroups32, a); - default: - UNREACHABLE(); - } - } - - U128 VectorReduceAdd(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorReduceAdd8, a); - case 16: - return Inst(Opcode::VectorReduceAdd16, a); - case 32: - return Inst(Opcode::VectorReduceAdd32, a); - case 64: - return Inst(Opcode::VectorReduceAdd64, a); - } - - UNREACHABLE(); - } - - U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount) { - ASSERT(amount < esize); - - if (amount == 0) { - return a; - } - - return VectorOr(VectorLogicalShiftLeft(esize, a, amount), - VectorLogicalShiftRight(esize, a, static_cast(esize - amount))); - } - - U128 VectorRotateRight(size_t esize, const U128& a, u8 amount) { - ASSERT(amount < esize); - - if (amount == 0) { - return a; - } - - return VectorOr(VectorLogicalShiftRight(esize, a, amount), - VectorLogicalShiftLeft(esize, a, static_cast(esize - amount))); - } - - U128 VectorRotateWholeVectorRight(const U128& a, u8 amount) { - ASSERT(amount % 32 == 0); - return Inst(Opcode::VectorRotateWholeVectorRight, a, Imm8(amount)); - } - - U128 VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorRoundingHalvingAddS8, a, b); - case 16: - return Inst(Opcode::VectorRoundingHalvingAddS16, a, b); - case 32: - return Inst(Opcode::VectorRoundingHalvingAddS32, a, b); - } - - UNREACHABLE(); - } - - U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorRoundingHalvingAddU8, a, b); - case 16: - return Inst(Opcode::VectorRoundingHalvingAddU16, a, b); - case 32: - return Inst(Opcode::VectorRoundingHalvingAddU32, a, b); - } - - UNREACHABLE(); - } - - U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorRoundingShiftLeftS8, a, b); - case 16: - return Inst(Opcode::VectorRoundingShiftLeftS16, a, b); - case 32: - return Inst(Opcode::VectorRoundingShiftLeftS32, a, b); - case 64: - return Inst(Opcode::VectorRoundingShiftLeftS64, a, b); - } - - UNREACHABLE(); - } - - U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorRoundingShiftLeftU8, a, b); - case 16: - return Inst(Opcode::VectorRoundingShiftLeftU16, a, b); - case 32: - return Inst(Opcode::VectorRoundingShiftLeftU32, a, b); - case 64: - return Inst(Opcode::VectorRoundingShiftLeftU64, a, b); - } - - UNREACHABLE(); - } - - U128 VectorSignExtend(size_t original_esize, const U128& a) { - switch (original_esize) { - case 8: - return Inst(Opcode::VectorSignExtend8, a); - case 16: - return Inst(Opcode::VectorSignExtend16, a); - case 32: - return Inst(Opcode::VectorSignExtend32, a); - case 64: - return Inst(Opcode::VectorSignExtend64, a); - } - UNREACHABLE(); - } - - U128 VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedAbsoluteDifference8, a, b); - case 16: - return Inst(Opcode::VectorSignedAbsoluteDifference16, a, b); - case 32: - return Inst(Opcode::VectorSignedAbsoluteDifference32, a, b); - } - UNREACHABLE(); - } - - UpperAndLower VectorSignedMultiply(size_t esize, const U128& a, const U128& b) { - const Value multiply = [&] { - switch (esize) { - case 16: - return Inst(Opcode::VectorSignedMultiply16, a, b); - case 32: - return Inst(Opcode::VectorSignedMultiply32, a, b); - } - UNREACHABLE(); - }(); - - return { - Inst(Opcode::GetUpperFromOp, multiply), - Inst(Opcode::GetLowerFromOp, multiply), - }; - } - - U128 VectorSignedSaturatedAbs(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedAbs8, a); - case 16: - return Inst(Opcode::VectorSignedSaturatedAbs16, a); - case 32: - return Inst(Opcode::VectorSignedSaturatedAbs32, a); - case 64: - return Inst(Opcode::VectorSignedSaturatedAbs64, a); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned8, a, b); - case 16: - return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned32, a, b); - case 64: - return Inst(Opcode::VectorSignedSaturatedAccumulateUnsigned64, a, b); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedDoublingMultiplyHigh(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 16: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHigh16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHigh32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorSignedSaturatedDoublingMultiplyHighRounding(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 16: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyHighRounding32, a, b); - default: - UNREACHABLE(); - } - } - - U128 VectorSignedSaturatedDoublingMultiplyLong(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 16: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyLong16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedDoublingMultiplyLong32, a, b); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a) { - switch (original_esize) { - case 16: - return Inst(Opcode::VectorSignedSaturatedNarrowToSigned16, a); - case 32: - return Inst(Opcode::VectorSignedSaturatedNarrowToSigned32, a); - case 64: - return Inst(Opcode::VectorSignedSaturatedNarrowToSigned64, a); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a) { - switch (original_esize) { - case 16: - return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned16, a); - case 32: - return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned32, a); - case 64: - return Inst(Opcode::VectorSignedSaturatedNarrowToUnsigned64, a); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedNeg(size_t esize, const U128& a) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedNeg8, a); - case 16: - return Inst(Opcode::VectorSignedSaturatedNeg16, a); - case 32: - return Inst(Opcode::VectorSignedSaturatedNeg32, a); - case 64: - return Inst(Opcode::VectorSignedSaturatedNeg64, a); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedShiftLeft8, a, b); - case 16: - return Inst(Opcode::VectorSignedSaturatedShiftLeft16, a, b); - case 32: - return Inst(Opcode::VectorSignedSaturatedShiftLeft32, a, b); - case 64: - return Inst(Opcode::VectorSignedSaturatedShiftLeft64, a, b); - } - UNREACHABLE(); - } - - U128 VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount) { - ASSERT(shift_amount < esize); - switch (esize) { - case 8: - return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned8, a, Imm8(shift_amount)); - case 16: - return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned16, a, Imm8(shift_amount)); - case 32: - return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned32, a, Imm8(shift_amount)); - case 64: - return Inst(Opcode::VectorSignedSaturatedShiftLeftUnsigned64, a, Imm8(shift_amount)); - } - UNREACHABLE(); - } - - U128 VectorSub(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorSub8, a, b); - case 16: - return Inst(Opcode::VectorSub16, a, b); - case 32: - return Inst(Opcode::VectorSub32, a, b); - case 64: - return Inst(Opcode::VectorSub64, a, b); - } - UNREACHABLE(); - } - - Table VectorTable(std::vector values) { - ASSERT(values.size() >= 1 && values.size() <= 4); - values.resize(4); - return Inst
(Opcode::VectorTable, values[0], values[1], values[2], values[3]); - } - - Table VectorTable(std::vector values) { - ASSERT(values.size() >= 1 && values.size() <= 4); - values.resize(4); - return Inst
(Opcode::VectorTable, values[0], values[1], values[2], values[3]); - } - - U64 VectorTableLookup(const U64& defaults, const Table& table, const U64& indices) { - ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U64); - return Inst(Opcode::VectorTableLookup64, defaults, table, indices); - } - - U128 VectorTableLookup(const U128& defaults, const Table& table, const U128& indices) { - ASSERT(table.GetInst()->GetArg(0).GetType() == Type::U128); - return Inst(Opcode::VectorTableLookup128, defaults, table, indices); - } - - U128 VectorTranspose(size_t esize, const U128& a, const U128& b, bool part) { - switch (esize) { - case 8: - return Inst(Opcode::VectorTranspose8, a, b, Imm1(part)); - case 16: - return Inst(Opcode::VectorTranspose16, a, b, Imm1(part)); - case 32: - return Inst(Opcode::VectorTranspose32, a, b, Imm1(part)); - case 64: - return Inst(Opcode::VectorTranspose64, a, b, Imm1(part)); - } - UNREACHABLE(); - } - - U128 VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorUnsignedAbsoluteDifference8, a, b); - case 16: - return Inst(Opcode::VectorUnsignedAbsoluteDifference16, a, b); - case 32: - return Inst(Opcode::VectorUnsignedAbsoluteDifference32, a, b); - } - UNREACHABLE(); - } - - U128 VectorUnsignedRecipEstimate(const U128& a) { - return Inst(Opcode::VectorUnsignedRecipEstimate, a); - } - - U128 VectorUnsignedRecipSqrtEstimate(const U128& a) { - return Inst(Opcode::VectorUnsignedRecipSqrtEstimate, a); - } - - U128 VectorUnsignedSaturatedAccumulateSigned(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned8, a, b); - case 16: - return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned16, a, b); - case 32: - return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned32, a, b); - case 64: - return Inst(Opcode::VectorUnsignedSaturatedAccumulateSigned64, a, b); - } - UNREACHABLE(); - } - - U128 VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) { - switch (esize) { - case 16: - return Inst(Opcode::VectorUnsignedSaturatedNarrow16, a); - case 32: - return Inst(Opcode::VectorUnsignedSaturatedNarrow32, a); - case 64: - return Inst(Opcode::VectorUnsignedSaturatedNarrow64, a); - } - UNREACHABLE(); - } - - U128 VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) { - switch (esize) { - case 8: - return Inst(Opcode::VectorUnsignedSaturatedShiftLeft8, a, b); - case 16: - return Inst(Opcode::VectorUnsignedSaturatedShiftLeft16, a, b); - case 32: - return Inst(Opcode::VectorUnsignedSaturatedShiftLeft32, a, b); - case 64: - return Inst(Opcode::VectorUnsignedSaturatedShiftLeft64, a, b); - } - UNREACHABLE(); - } - - U128 VectorZeroExtend(size_t original_esize, const U128& a) { - switch (original_esize) { - case 8: - return Inst(Opcode::VectorZeroExtend8, a); - case 16: - return Inst(Opcode::VectorZeroExtend16, a); - case 32: - return Inst(Opcode::VectorZeroExtend32, a); - case 64: - return Inst(Opcode::VectorZeroExtend64, a); - } - UNREACHABLE(); - } - - U128 VectorZeroUpper(const U128& a) { - return Inst(Opcode::VectorZeroUpper, a); - } - - U128 ZeroVector() { - return Inst(Opcode::ZeroVector); - } - - U16U32U64 FPAbs(const U16U32U64& a) { - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPAbs16, a); - case Type::U32: - return Inst(Opcode::FPAbs32, a); - case Type::U64: - return Inst(Opcode::FPAbs64, a); - default: - UNREACHABLE(); - } - } - - U32U64 FPAdd(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPAdd32, a, b); - case Type::U64: - return Inst(Opcode::FPAdd64, a, b); - default: - UNREACHABLE(); - } - } - - NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan) { - ASSERT(a.GetType() == b.GetType()); - - const IR::U1 exc_on_qnan_imm = Imm1(exc_on_qnan); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPCompare32, a, b, exc_on_qnan_imm); - case Type::U64: - return Inst(Opcode::FPCompare64, a, b, exc_on_qnan_imm); - default: - UNREACHABLE(); - } - } - - U32U64 FPDiv(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPDiv32, a, b); - case Type::U64: - return Inst(Opcode::FPDiv64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPMax(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMax32, a, b); - case Type::U64: - return Inst(Opcode::FPMax64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMaxNumeric32, a, b); - case Type::U64: - return Inst(Opcode::FPMaxNumeric64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPMin(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMin32, a, b); - case Type::U64: - return Inst(Opcode::FPMin64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPMinNumeric(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMinNumeric32, a, b); - case Type::U64: - return Inst(Opcode::FPMinNumeric64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPMul(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMul32, a, b); - case Type::U64: - return Inst(Opcode::FPMul64, a, b); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPMulAdd16, a, b, c); - case Type::U32: - return Inst(Opcode::FPMulAdd32, a, b, c); - case Type::U64: - return Inst(Opcode::FPMulAdd64, a, b, c); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPMulSub(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPMulSub16, a, b, c); - case Type::U32: - return Inst(Opcode::FPMulSub32, a, b, c); - case Type::U64: - return Inst(Opcode::FPMulSub64, a, b, c); - default: - UNREACHABLE(); - } - } - - U32U64 FPMulX(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPMulX32, a, b); - case Type::U64: - return Inst(Opcode::FPMulX64, a, b); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPNeg(const U16U32U64& a) { - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPNeg16, a); - case Type::U32: - return Inst(Opcode::FPNeg32, a); - case Type::U64: - return Inst(Opcode::FPNeg64, a); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRecipEstimate(const U16U32U64& a) { - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRecipEstimate16, a); - case Type::U32: - return Inst(Opcode::FPRecipEstimate32, a); - case Type::U64: - return Inst(Opcode::FPRecipEstimate64, a); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRecipExponent(const U16U32U64& a) { - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRecipExponent16, a); - case Type::U32: - return Inst(Opcode::FPRecipExponent32, a); - case Type::U64: - return Inst(Opcode::FPRecipExponent64, a); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRecipStepFused16, a, b); - case Type::U32: - return Inst(Opcode::FPRecipStepFused32, a, b); - case Type::U64: - return Inst(Opcode::FPRecipStepFused64, a, b); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact) { - const u8 rounding_value = static_cast(rounding); - const IR::U1 exact_imm = Imm1(exact); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRoundInt16, a, rounding_value, exact_imm); - case Type::U32: - return Inst(Opcode::FPRoundInt32, a, rounding_value, exact_imm); - case Type::U64: - return Inst(Opcode::FPRoundInt64, a, rounding_value, exact_imm); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRSqrtEstimate(const U16U32U64& a) { - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRSqrtEstimate16, a); - case Type::U32: - return Inst(Opcode::FPRSqrtEstimate32, a); - case Type::U64: - return Inst(Opcode::FPRSqrtEstimate64, a); - default: - UNREACHABLE(); - } - } - - U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPRSqrtStepFused16, a, b); - case Type::U32: - return Inst(Opcode::FPRSqrtStepFused32, a, b); - case Type::U64: - return Inst(Opcode::FPRSqrtStepFused64, a, b); - default: - UNREACHABLE(); - } - } - - U32U64 FPSqrt(const U32U64& a) { - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPSqrt32, a); - case Type::U64: - return Inst(Opcode::FPSqrt64, a); - default: - UNREACHABLE(); - } - } - - U32U64 FPSub(const U32U64& a, const U32U64& b) { - ASSERT(a.GetType() == b.GetType()); - - switch (a.GetType()) { - case Type::U32: - return Inst(Opcode::FPSub32, a, b); - case Type::U64: - return Inst(Opcode::FPSub64, a, b); - default: - UNREACHABLE(); - } - } - - U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPDoubleToHalf, a, Imm8(static_cast(rounding))); - } - - U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPDoubleToSingle, a, Imm8(static_cast(rounding))); - } - - U64 FPHalfToDouble(const U16& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPHalfToDouble, a, Imm8(static_cast(rounding))); - } - - U32 FPHalfToSingle(const U16& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPHalfToSingle, a, Imm8(static_cast(rounding))); - } - - U64 FPSingleToDouble(const U32& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPSingleToDouble, a, Imm8(static_cast(rounding))); - } - - U16 FPSingleToHalf(const U32& a, FP::RoundingMode rounding) { - return Inst(Opcode::FPSingleToHalf, a, Imm8(static_cast(rounding))); - } - - U16 FPToFixedS16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 16); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedS16, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedS16, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedS16, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U32 FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 32); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedS32, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedS32, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedS32, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U64 FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 64); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedS64, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedS64, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedS64, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U16 FPToFixedU16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 16); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedU16, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedU16, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedU16, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U32 FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 32); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedU32, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedU32, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedU32, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U64 FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= 64); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPHalfToFixedU64, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPSingleToFixedU64, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPDoubleToFixedU64, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U32 FPSignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); - - const IR::U8 fbits_imm = Imm8(static_cast(fbits)); - const IR::U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPFixedS16ToSingle, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPFixedS32ToSingle, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPFixedS64ToSingle, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U32 FPUnsignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); - - const IR::U8 fbits_imm = Imm8(static_cast(fbits)); - const IR::U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPFixedU16ToSingle, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPFixedU32ToSingle, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPFixedU64ToSingle, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U64 FPSignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); - - const IR::U8 fbits_imm = Imm8(static_cast(fbits)); - const IR::U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPFixedS16ToDouble, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPFixedS32ToDouble, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPFixedS64ToDouble, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U64 FPUnsignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding) { - ASSERT(fbits <= (a.GetType() == Type::U16 ? 16 : (a.GetType() == Type::U32 ? 32 : 64))); - - const IR::U8 fbits_imm = Imm8(static_cast(fbits)); - const IR::U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (a.GetType()) { - case Type::U16: - return Inst(Opcode::FPFixedU16ToDouble, a, fbits_imm, rounding_imm); - case Type::U32: - return Inst(Opcode::FPFixedU32ToDouble, a, fbits_imm, rounding_imm); - case Type::U64: - return Inst(Opcode::FPFixedU64ToDouble, a, fbits_imm, rounding_imm); - default: - UNREACHABLE(); - } - } - - U128 FPVectorAbs(size_t esize, const U128& a) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorAbs16, a); - case 32: - return Inst(Opcode::FPVectorAbs32, a); - case 64: - return Inst(Opcode::FPVectorAbs64, a); - } - UNREACHABLE(); - } - - U128 FPVectorAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorAdd32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorAdd64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorDiv(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorDiv32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorDiv64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorEqual16, a, b, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorEqual32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorEqual64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(esize == 32); - return Inst(Opcode::FPVectorFromHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - } - - U128 FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); - switch (esize) { - case 32: - return Inst(Opcode::FPVectorFromSignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); - switch (esize) { - case 32: - return Inst(Opcode::FPVectorFromUnsignedFixed32, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast(fbits)), Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorGreater(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorGreater32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorGreater64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorGreaterEqual32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorGreaterEqual64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMax(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMax32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMax64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMaxNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMaxNumeric32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMaxNumeric64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMin(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMin32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMin64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMinNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMinNumeric32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMinNumeric64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMul(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMul32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMul64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorMulAdd16, a, b, c, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorMulAdd32, a, b, c, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMulAdd64, a, b, c, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorMulX(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorMulX32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorMulX64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorNeg(size_t esize, const U128& a) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorNeg16, a); - case 32: - return Inst(Opcode::FPVectorNeg32, a); - case 64: - return Inst(Opcode::FPVectorNeg64, a); - } - UNREACHABLE(); - } - - U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorPairedAdd32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorPairedAdd64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorPairedAddLower32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorPairedAddLower64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorRecipEstimate16, a, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorRecipEstimate32, a, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorRecipStepFused16, a, b, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorRecipStepFused32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorRecipStepFused64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact, bool fpcr_controlled = true) { - const IR::U8 rounding_imm = Imm8(static_cast(rounding)); - const IR::U1 exact_imm = Imm1(exact); - - switch (esize) { - case 16: - return Inst(Opcode::FPVectorRoundInt16, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorRoundInt32, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorRoundInt64, operand, rounding_imm, exact_imm, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorRSqrtEstimate16, a, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorRSqrtEstimate32, a, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 16: - return Inst(Opcode::FPVectorRSqrtStepFused16, a, b, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorRSqrtStepFused32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorRSqrtStepFused64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorSqrt(size_t esize, const U128& a, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorSqrt32, a, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorSqrt64, a, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true) { - switch (esize) { - case 32: - return Inst(Opcode::FPVectorSub32, a, b, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled)); - } - UNREACHABLE(); - } - - U128 FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(esize == 32); - return Inst(Opcode::FPVectorToHalf32, a, Imm8(static_cast(rounding)), Imm1(fpcr_controlled)); - } - - U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (esize) { - case 16: - return Inst(Opcode::FPVectorToSignedFixed16, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorToSignedFixed32, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorToSignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - } - - UNREACHABLE(); - } - - U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true) { - ASSERT(fbits <= esize); - - const U8 fbits_imm = Imm8(static_cast(fbits)); - const U8 rounding_imm = Imm8(static_cast(rounding)); - - switch (esize) { - case 16: - return Inst(Opcode::FPVectorToUnsignedFixed16, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - case 32: - return Inst(Opcode::FPVectorToUnsignedFixed32, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - case 64: - return Inst(Opcode::FPVectorToUnsignedFixed64, a, fbits_imm, rounding_imm, Imm1(fpcr_controlled)); - } - - UNREACHABLE(); - } - - void Breakpoint() { - Inst(Opcode::Breakpoint); - } - - void CallHostFunction(void (*fn)(void)) { - Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), Value{}, Value{}, Value{}); - } - - void CallHostFunction(void (*fn)(u64), const U64& arg1) { - Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, Value{}, Value{}); - } - - void CallHostFunction(void (*fn)(u64, u64), const U64& arg1, const U64& arg2) { - Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2, Value{}); - } - - void CallHostFunction(void (*fn)(u64, u64, u64), const U64& arg1, const U64& arg2, const U64& arg3) { - Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2, arg3); - } - - void SetTerm(const Terminal& terminal) { - block.SetTerminal(terminal); - } + U1 Imm1(bool value) const; + U8 Imm8(u8 value) const; + U16 Imm16(u16 value) const; + U32 Imm32(u32 value) const; + U64 Imm64(u64 value) const; + + void PushRSB(const LocationDescriptor& return_location); + + U64 Pack2x32To1x64(const U32& lo, const U32& hi); + U128 Pack2x64To1x128(const U64& lo, const U64& hi); + UAny LeastSignificant(size_t bitsize, const U32U64& value); + U32 LeastSignificantWord(const U64& value); + U16 LeastSignificantHalf(U32U64 value); + U8 LeastSignificantByte(U32U64 value); + ResultAndCarry MostSignificantWord(const U64& value); + U1 MostSignificantBit(const U32& value); + U1 IsZero(const U32& value); + U1 IsZero(const U64& value); + U1 IsZero(const U32U64& value); + U1 TestBit(const U32U64& value, const U8& bit); + U32 ConditionalSelect(Cond cond, const U32& a, const U32& b); + U64 ConditionalSelect(Cond cond, const U64& a, const U64& b); + NZCV ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b); + U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b); + + U1 GetCFlagFromNZCV(const NZCV& nzcv); + NZCV NZCVFromPackedFlags(const U32& a); + // This pseudo-instruction may only be added to instructions that support it. + NZCV NZCVFrom(const Value& value); + + ResultAndCarry LogicalShiftLeft(const U32& value_in, const U8& shift_amount, const U1& carry_in); + ResultAndCarry LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in); + ResultAndCarry ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in); + ResultAndCarry RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in); + U32U64 LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount); + U32U64 LogicalShiftRight(const U32U64& value_in, const U8& shift_amount); + U32U64 ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount); + U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount); + U32U64 LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount); + U32U64 LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount); + U32U64 ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount); + U32U64 RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount); + ResultAndCarry RotateRightExtended(const U32& value_in, const U1& carry_in); + U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in); + U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in); + U32U64 Add(const U32U64& a, const U32U64& b); + U32U64 Sub(const U32U64& a, const U32U64& b); + U32U64 Mul(const U32U64& a, const U32U64& b); + U64 UnsignedMultiplyHigh(const U64& a, const U64& b); + U64 SignedMultiplyHigh(const U64& a, const U64& b); + U32U64 UnsignedDiv(const U32U64& a, const U32U64& b); + U32U64 SignedDiv(const U32U64& a, const U32U64& b); + U32U64 And(const U32U64& a, const U32U64& b); + U32U64 AndNot(const U32U64& a, const U32U64& b); + U32U64 Eor(const U32U64& a, const U32U64& b); + U32U64 Or(const U32U64& a, const U32U64& b); + U32U64 Not(const U32U64& a); + U32 SignExtendToWord(const UAny& a); + U64 SignExtendToLong(const UAny& a); + U32 SignExtendByteToWord(const U8& a); + U32 SignExtendHalfToWord(const U16& a); + U64 SignExtendWordToLong(const U32& a); + U32 ZeroExtendToWord(const UAny& a); + U64 ZeroExtendToLong(const UAny& a); + U128 ZeroExtendToQuad(const UAny& a); + U32 ZeroExtendByteToWord(const U8& a); + U32 ZeroExtendHalfToWord(const U16& a); + U64 ZeroExtendWordToLong(const U32& a); + U32 IndeterminateExtendToWord(const UAny& a); + U64 IndeterminateExtendToLong(const UAny& a); + U32 ByteReverseWord(const U32& a); + U16 ByteReverseHalf(const U16& a); + U64 ByteReverseDual(const U64& a); + U32U64 CountLeadingZeros(const U32U64& a); + U32U64 ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb); + U32U64 ReplicateBit(const U32U64& a, u8 bit); + U32U64 MaxSigned(const U32U64& a, const U32U64& b); + U32U64 MaxUnsigned(const U32U64& a, const U32U64& b); + U32U64 MinSigned(const U32U64& a, const U32U64& b); + U32U64 MinUnsigned(const U32U64& a, const U32U64& b); + + ResultAndOverflow SignedSaturatedAddWithFlag(const U32& a, const U32& b); + ResultAndOverflow SignedSaturatedSubWithFlag(const U32& a, const U32& b); + ResultAndOverflow SignedSaturation(const U32& a, size_t bit_size_to_saturate_to); + ResultAndOverflow UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to); + + UAny SignedSaturatedAdd(const UAny& a, const UAny& b); + UAny SignedSaturatedDoublingMultiplyReturnHigh(const UAny& a, const UAny& b); + UAny SignedSaturatedSub(const UAny& a, const UAny& b); + UAny UnsignedSaturatedAdd(const UAny& a, const UAny& b); + UAny UnsignedSaturatedSub(const UAny& a, const UAny& b); + + U128 VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b); + U128 VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b); + U128 VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b); + + ResultAndGE PackedAddU8(const U32& a, const U32& b); + ResultAndGE PackedAddS8(const U32& a, const U32& b); + ResultAndGE PackedAddU16(const U32& a, const U32& b); + ResultAndGE PackedAddS16(const U32& a, const U32& b); + ResultAndGE PackedSubU8(const U32& a, const U32& b); + ResultAndGE PackedSubS8(const U32& a, const U32& b); + ResultAndGE PackedSubU16(const U32& a, const U32& b); + ResultAndGE PackedSubS16(const U32& a, const U32& b); + ResultAndGE PackedAddSubU16(const U32& a, const U32& b); + ResultAndGE PackedAddSubS16(const U32& a, const U32& b); + ResultAndGE PackedSubAddU16(const U32& a, const U32& b); + ResultAndGE PackedSubAddS16(const U32& a, const U32& b); + U32 PackedHalvingAddU8(const U32& a, const U32& b); + U32 PackedHalvingAddS8(const U32& a, const U32& b); + U32 PackedHalvingSubU8(const U32& a, const U32& b); + U32 PackedHalvingSubS8(const U32& a, const U32& b); + U32 PackedHalvingAddU16(const U32& a, const U32& b); + U32 PackedHalvingAddS16(const U32& a, const U32& b); + U32 PackedHalvingSubU16(const U32& a, const U32& b); + U32 PackedHalvingSubS16(const U32& a, const U32& b); + U32 PackedHalvingAddSubU16(const U32& a, const U32& b); + U32 PackedHalvingAddSubS16(const U32& a, const U32& b); + U32 PackedHalvingSubAddU16(const U32& a, const U32& b); + U32 PackedHalvingSubAddS16(const U32& a, const U32& b); + U32 PackedSaturatedAddU8(const U32& a, const U32& b); + U32 PackedSaturatedAddS8(const U32& a, const U32& b); + U32 PackedSaturatedSubU8(const U32& a, const U32& b); + U32 PackedSaturatedSubS8(const U32& a, const U32& b); + U32 PackedSaturatedAddU16(const U32& a, const U32& b); + U32 PackedSaturatedAddS16(const U32& a, const U32& b); + U32 PackedSaturatedSubU16(const U32& a, const U32& b); + U32 PackedSaturatedSubS16(const U32& a, const U32& b); + U32 PackedAbsDiffSumU8(const U32& a, const U32& b); + U32 PackedSelect(const U32& ge, const U32& a, const U32& b); + + U32 CRC32Castagnoli8(const U32& a, const U32& b); + U32 CRC32Castagnoli16(const U32& a, const U32& b); + U32 CRC32Castagnoli32(const U32& a, const U32& b); + U32 CRC32Castagnoli64(const U32& a, const U64& b); + U32 CRC32ISO8(const U32& a, const U32& b); + U32 CRC32ISO16(const U32& a, const U32& b); + U32 CRC32ISO32(const U32& a, const U32& b); + U32 CRC32ISO64(const U32& a, const U64& b); + + U128 AESDecryptSingleRound(const U128& a); + U128 AESEncryptSingleRound(const U128& a); + U128 AESInverseMixColumns(const U128& a); + U128 AESMixColumns(const U128& a); + + U8 SM4AccessSubstitutionBox(const U8& a); + + U128 SHA256Hash(const U128& x, const U128& y, const U128& w, bool part1); + U128 SHA256MessageSchedule0(const U128& x, const U128& y); + U128 SHA256MessageSchedule1(const U128& x, const U128& y, const U128& z); + + UAny VectorGetElement(size_t esize, const U128& a, size_t index); + U128 VectorSetElement(size_t esize, const U128& a, size_t index, const UAny& elem); + U128 VectorAbs(size_t esize, const U128& a); + U128 VectorAdd(size_t esize, const U128& a, const U128& b); + U128 VectorAnd(const U128& a, const U128& b); + U128 VectorAndNot(const U128& a, const U128& b); + U128 VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount); + U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b); + U128 VectorBroadcast(size_t esize, const UAny& a); + U128 VectorBroadcastLower(size_t esize, const UAny& a); + U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index); + U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index); + U128 VectorCountLeadingZeros(size_t esize, const U128& a); + U128 VectorEor(const U128& a, const U128& b); + U128 VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b); + U128 VectorDeinterleaveEvenLower(size_t esize, const U128& a, const U128& b); + U128 VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b); + U128 VectorDeinterleaveOddLower(size_t esize, const U128& a, const U128& b); + U128 VectorEqual(size_t esize, const U128& a, const U128& b); + U128 VectorExtract(const U128& a, const U128& b, size_t position); + U128 VectorExtractLower(const U128& a, const U128& b, size_t position); + U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b); + U128 VectorGreaterEqualUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorGreaterSigned(size_t esize, const U128& a, const U128& b); + U128 VectorGreaterUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorHalvingAddSigned(size_t esize, const U128& a, const U128& b); + U128 VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b); + U128 VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b); + U128 VectorInterleaveUpper(size_t esize, const U128& a, const U128& b); + U128 VectorLessEqualSigned(size_t esize, const U128& a, const U128& b); + U128 VectorLessEqualUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorLessSigned(size_t esize, const U128& a, const U128& b); + U128 VectorLessUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount); + U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount); + U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b); + U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b); + U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorMinSigned(size_t esize, const U128& a, const U128& b); + U128 VectorMinUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorMultiply(size_t esize, const U128& a, const U128& b); + U128 VectorMultiplySignedWiden(size_t esize, const U128& a, const U128& b); + U128 VectorMultiplyUnsignedWiden(size_t esize, const U128& a, const U128& b); + U128 VectorNarrow(size_t original_esize, const U128& a); + U128 VectorNot(const U128& a); + U128 VectorOr(const U128& a, const U128& b); + U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b); + U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b); + U128 VectorPairedAddSignedWiden(size_t original_esize, const U128& a); + U128 VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a); + U128 VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMaxUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMinSigned(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMinUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMaxSignedLower(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMaxUnsignedLower(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMinSignedLower(size_t esize, const U128& a, const U128& b); + U128 VectorPairedMinUnsignedLower(size_t esize, const U128& a, const U128& b); + U128 VectorPolynomialMultiply(const U128& a, const U128& b); + U128 VectorPolynomialMultiplyLong(size_t esize, const U128& a, const U128& b); + U128 VectorPopulationCount(const U128& a); + U128 VectorReverseBits(const U128& a); + U128 VectorReverseElementsInHalfGroups(size_t esize, const U128& a); + U128 VectorReverseElementsInWordGroups(size_t esize, const U128& a); + U128 VectorReverseElementsInLongGroups(size_t esize, const U128& a); + U128 VectorReduceAdd(size_t esize, const U128& a); + U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount); + U128 VectorRotateRight(size_t esize, const U128& a, u8 amount); + U128 VectorRotateWholeVectorRight(const U128& a, u8 amount); + U128 VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b); + U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b); + U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorSignExtend(size_t original_esize, const U128& a); + U128 VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b); + UpperAndLower VectorSignedMultiply(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedAbs(size_t esize, const U128& a); + U128 VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedDoublingMultiplyHigh(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedDoublingMultiplyHighRounding(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedDoublingMultiplyLong(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a); + U128 VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a); + U128 VectorSignedSaturatedNeg(size_t esize, const U128& a); + U128 VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b); + U128 VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, u8 shift_amount); + U128 VectorSub(size_t esize, const U128& a, const U128& b); + Table VectorTable(std::vector values); + Table VectorTable(std::vector values); + U64 VectorTableLookup(const U64& defaults, const Table& table, const U64& indices); + U128 VectorTableLookup(const U128& defaults, const Table& table, const U128& indices); + U128 VectorTranspose(size_t esize, const U128& a, const U128& b, bool part); + U128 VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b); + U128 VectorUnsignedRecipEstimate(const U128& a); + U128 VectorUnsignedRecipSqrtEstimate(const U128& a); + U128 VectorUnsignedSaturatedAccumulateSigned(size_t esize, const U128& a, const U128& b); + U128 VectorUnsignedSaturatedNarrow(size_t esize, const U128& a); + U128 VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b); + U128 VectorZeroExtend(size_t original_esize, const U128& a); + U128 VectorZeroUpper(const U128& a); + U128 ZeroVector(); + + U16U32U64 FPAbs(const U16U32U64& a); + U32U64 FPAdd(const U32U64& a, const U32U64& b); + NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan); + U32U64 FPDiv(const U32U64& a, const U32U64& b); + U32U64 FPMax(const U32U64& a, const U32U64& b); + U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b); + U32U64 FPMin(const U32U64& a, const U32U64& b); + U32U64 FPMinNumeric(const U32U64& a, const U32U64& b); + U32U64 FPMul(const U32U64& a, const U32U64& b); + U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2); + U16U32U64 FPMulSub(const U16U32U64& minuend, const U16U32U64& op1, const U16U32U64& op2); + U32U64 FPMulX(const U32U64& a, const U32U64& b); + U16U32U64 FPNeg(const U16U32U64& a); + U16U32U64 FPRecipEstimate(const U16U32U64& a); + U16U32U64 FPRecipExponent(const U16U32U64& a); + U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b); + U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact); + U16U32U64 FPRSqrtEstimate(const U16U32U64& a); + U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b); + U32U64 FPSqrt(const U32U64& a); + U32U64 FPSub(const U32U64& a, const U32U64& b); + U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding); + U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding); + U64 FPHalfToDouble(const U16& a, FP::RoundingMode rounding); + U32 FPHalfToSingle(const U16& a, FP::RoundingMode rounding); + U16 FPSingleToHalf(const U32& a, FP::RoundingMode rounding); + U64 FPSingleToDouble(const U32& a, FP::RoundingMode rounding); + U16 FPToFixedS16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U32 FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U64 FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U16 FPToFixedU16(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U32 FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U64 FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U32 FPSignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U32 FPUnsignedFixedToSingle(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U64 FPSignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + U64 FPUnsignedFixedToDouble(const U16U32U64& a, size_t fbits, FP::RoundingMode rounding); + + U128 FPVectorAbs(size_t esize, const U128& a); + U128 FPVectorAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorDiv(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorFromHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true); + U128 FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true); + U128 FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true); + U128 FPVectorGreater(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMax(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMaxNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMin(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMinNumeric(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMul(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorMulAdd(size_t esize, const U128& addend, const U128& op1, const U128& op2, bool fpcr_controlled = true); + U128 FPVectorMulX(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorNeg(size_t esize, const U128& a); + U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); + U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact, bool fpcr_controlled = true); + U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); + U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorSqrt(size_t esize, const U128& a, bool fpcr_controlled = true); + U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); + U128 FPVectorToHalf(size_t esize, const U128& a, FP::RoundingMode rounding, bool fpcr_controlled = true); + U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true); + U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding, bool fpcr_controlled = true); + + void Breakpoint(); + void CallHostFunction(void (*fn)(void)); + void CallHostFunction(void (*fn)(u64), const U64& arg1); + void CallHostFunction(void (*fn)(u64, u64), const U64& arg1, const U64& arg2); + void CallHostFunction(void (*fn)(u64, u64, u64), const U64& arg1, const U64& arg2, const U64& arg3); + + void SetTerm(const Terminal& terminal); void SetInsertionPointBefore(IR::Inst* new_insertion_point) { insertion_point = IR::Block::iterator{*new_insertion_point}; diff --git a/externals/dynarmic/src/dynarmic/ir/location_descriptor.h b/externals/dynarmic/src/dynarmic/ir/location_descriptor.h index 5c7c954d38..48e5e32bb1 100644 --- a/externals/dynarmic/src/dynarmic/ir/location_descriptor.h +++ b/externals/dynarmic/src/dynarmic/ir/location_descriptor.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/externals/dynarmic/src/dynarmic/ir/microinstruction.cpp b/externals/dynarmic/src/dynarmic/ir/microinstruction.cpp index f0ea4ac2c2..3f67a3ad78 100644 --- a/externals/dynarmic/src/dynarmic/ir/microinstruction.cpp +++ b/externals/dynarmic/src/dynarmic/ir/microinstruction.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" diff --git a/externals/dynarmic/src/dynarmic/ir/microinstruction.h b/externals/dynarmic/src/dynarmic/ir/microinstruction.h index bc5a355793..a26a9d80b3 100644 --- a/externals/dynarmic/src/dynarmic/ir/microinstruction.h +++ b/externals/dynarmic/src/dynarmic/ir/microinstruction.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/ir/value.h" #include "dynarmic/ir/opcodes.h" diff --git a/externals/dynarmic/src/dynarmic/ir/opcodes.h b/externals/dynarmic/src/dynarmic/ir/opcodes.h index c11ad549da..2af7a9b24f 100644 --- a/externals/dynarmic/src/dynarmic/ir/opcodes.h +++ b/externals/dynarmic/src/dynarmic/ir/opcodes.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/externals/dynarmic/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp b/externals/dynarmic/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp index 499b38b120..06e159ba48 100644 --- a/externals/dynarmic/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp +++ b/externals/dynarmic/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,8 +7,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/frontend/A32/a32_ir_emitter.h" #include "dynarmic/frontend/A32/a32_types.h" diff --git a/externals/dynarmic/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp b/externals/dynarmic/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp index 53e3b27176..4034eebfc3 100644 --- a/externals/dynarmic/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp +++ b/externals/dynarmic/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/ir/basic_block.h" diff --git a/externals/dynarmic/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp b/externals/dynarmic/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp index 25b7ef0ff1..00a0e1b672 100644 --- a/externals/dynarmic/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp +++ b/externals/dynarmic/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp @@ -1,13 +1,10 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD */ #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/translate/a64_translate.h" diff --git a/externals/dynarmic/src/dynarmic/ir/opt/constant_propagation_pass.cpp b/externals/dynarmic/src/dynarmic/ir/opt/constant_propagation_pass.cpp index 86ebca87d2..83530fc453 100644 --- a/externals/dynarmic/src/dynarmic/ir/opt/constant_propagation_pass.cpp +++ b/externals/dynarmic/src/dynarmic/ir/opt/constant_propagation_pass.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,10 +5,10 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/safe_ops.h" #include "dynarmic/ir/basic_block.h" diff --git a/externals/dynarmic/src/dynarmic/ir/opt/verification_pass.cpp b/externals/dynarmic/src/dynarmic/ir/opt/verification_pass.cpp index c6c2cff231..9252997fcf 100644 --- a/externals/dynarmic/src/dynarmic/ir/opt/verification_pass.cpp +++ b/externals/dynarmic/src/dynarmic/ir/opt/verification_pass.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,8 +6,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include #include "dynarmic/ir/basic_block.h" diff --git a/externals/dynarmic/src/dynarmic/ir/terminal.h b/externals/dynarmic/src/dynarmic/ir/terminal.h index 130dfc6574..d437ffd5b6 100644 --- a/externals/dynarmic/src/dynarmic/ir/terminal.h +++ b/externals/dynarmic/src/dynarmic/ir/terminal.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #pragma once #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/ir/cond.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/externals/dynarmic/src/dynarmic/ir/type.h b/externals/dynarmic/src/dynarmic/ir/type.h index 0aaf9d9414..65fe76dd65 100644 --- a/externals/dynarmic/src/dynarmic/ir/type.h +++ b/externals/dynarmic/src/dynarmic/ir/type.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/externals/dynarmic/src/dynarmic/ir/value.cpp b/externals/dynarmic/src/dynarmic/ir/value.cpp index 6f8a386827..957e78d8fa 100644 --- a/externals/dynarmic/src/dynarmic/ir/value.cpp +++ b/externals/dynarmic/src/dynarmic/ir/value.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "dynarmic/ir/value.h" -#include "dynarmic/common/assert.h" +#include #include #include "dynarmic/ir/microinstruction.h" diff --git a/externals/dynarmic/src/dynarmic/ir/value.h b/externals/dynarmic/src/dynarmic/ir/value.h index 4eca82ae94..e396641144 100644 --- a/externals/dynarmic/src/dynarmic/ir/value.h +++ b/externals/dynarmic/src/dynarmic/ir/value.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,8 +8,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/ir/type.h" diff --git a/externals/dynarmic/tests/A32/fuzz_arm.cpp b/externals/dynarmic/tests/A32/fuzz_arm.cpp index 9498f86d9b..cda424e27d 100644 --- a/externals/dynarmic/tests/A32/fuzz_arm.cpp +++ b/externals/dynarmic/tests/A32/fuzz_arm.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -18,7 +15,7 @@ #include #include #include -#include "dynarmic/common/common_types.h" +#include #include "../fuzz_util.h" #include "../rand_int.h" diff --git a/externals/dynarmic/tests/A32/fuzz_thumb.cpp b/externals/dynarmic/tests/A32/fuzz_thumb.cpp index dfd5672772..f13c5ee018 100644 --- a/externals/dynarmic/tests/A32/fuzz_thumb.cpp +++ b/externals/dynarmic/tests/A32/fuzz_thumb.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD @@ -17,7 +14,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "../rand_int.h" #include "../unicorn_emu/a32_unicorn.h" diff --git a/externals/dynarmic/tests/A32/test_arm_instructions.cpp b/externals/dynarmic/tests/A32/test_arm_instructions.cpp index 598f9d2248..3232f1a8f1 100644 --- a/externals/dynarmic/tests/A32/test_arm_instructions.cpp +++ b/externals/dynarmic/tests/A32/test_arm_instructions.cpp @@ -539,8 +539,7 @@ TEST_CASE("arm: Memory access (fastmem)", "[arm][A32]") { char* backing_memory = reinterpret_cast(std::align(page_size, memory_size, buffer_ptr, buffer_size_nconst)); A32FastmemTestEnv env{backing_memory}; - Dynarmic::A32::UserConfig config{}; - config.callbacks = &env; + Dynarmic::A32::UserConfig config{&env}; config.fastmem_pointer = reinterpret_cast(backing_memory); config.recompile_on_fastmem_failure = false; config.processor_id = 0; diff --git a/externals/dynarmic/tests/A32/test_thumb_instructions.cpp b/externals/dynarmic/tests/A32/test_thumb_instructions.cpp index b34e60749b..dda0fc46b5 100644 --- a/externals/dynarmic/tests/A32/test_thumb_instructions.cpp +++ b/externals/dynarmic/tests/A32/test_thumb_instructions.cpp @@ -1,13 +1,10 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2016 MerryMage * SPDX-License-Identifier: 0BSD */ #include -#include "dynarmic/common/common_types.h" +#include #include "./testenv.h" #include "dynarmic/interface/A32/a32.h" diff --git a/externals/dynarmic/tests/A32/testenv.h b/externals/dynarmic/tests/A32/testenv.h index b196c5e568..4345663b34 100644 --- a/externals/dynarmic/tests/A32/testenv.h +++ b/externals/dynarmic/tests/A32/testenv.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -14,8 +11,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/interface/A32/a32.h" diff --git a/externals/dynarmic/tests/A64/a64.cpp b/externals/dynarmic/tests/A64/a64.cpp index 801b01d555..246e61e122 100644 --- a/externals/dynarmic/tests/A64/a64.cpp +++ b/externals/dynarmic/tests/A64/a64.cpp @@ -15,9 +15,7 @@ using namespace oaknut::util; TEST_CASE("A64: ADD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2 env.code_mem.emplace_back(0x14000000); // B . @@ -38,9 +36,7 @@ TEST_CASE("A64: ADD", "[a64]") { TEST_CASE("A64: ADD{V,P}", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0E31B801); // ADDV b1, v0.8b env.code_mem.emplace_back(0x4E31B802); // ADDV b2, v0.16b @@ -66,9 +62,7 @@ TEST_CASE("A64: ADD{V,P}", "[a64]") { TEST_CASE("A64: CLZ", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.CLZ(V3.B16(), V0.B16()); @@ -90,9 +84,7 @@ TEST_CASE("A64: CLZ", "[a64]") { TEST_CASE("A64: UADDL{V,P}", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x2E303801); // UADDLV h1, v0.8b env.code_mem.emplace_back(0x6E303802); // UADDLV h2, v0.16b @@ -118,9 +110,7 @@ TEST_CASE("A64: UADDL{V,P}", "[a64]") { TEST_CASE("A64: SADDL{V,P}", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0E303801); // SADDLV h1, v0.8b env.code_mem.emplace_back(0x4E303802); // SADDLV h2, v0.16b @@ -146,9 +136,7 @@ TEST_CASE("A64: SADDL{V,P}", "[a64]") { TEST_CASE("A64: VQADD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x6e210c02); // UQADD v2.16b, v0.16b, v1.16b env.code_mem.emplace_back(0x4e210c03); // SQADD v3.16b, v0.16b, v1.16b @@ -179,9 +167,7 @@ TEST_CASE("A64: VQADD", "[a64]") { TEST_CASE("A64: VQSUB", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x6e212c02); // UQSUB v2.16b, v0.16b, v1.16b env.code_mem.emplace_back(0x4e212c03); // SQSUB v3.16b, v0.16b, v1.16b @@ -212,9 +198,7 @@ TEST_CASE("A64: VQSUB", "[a64]") { TEST_CASE("A64: REV", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xdac00c00); // REV X0, X0 env.code_mem.emplace_back(0x5ac00821); // REV W1, W1 @@ -234,9 +218,7 @@ TEST_CASE("A64: REV", "[a64]") { TEST_CASE("A64: REV32", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xdac00800); // REV32 X0, X0 env.code_mem.emplace_back(0x14000000); // B . @@ -252,9 +234,7 @@ TEST_CASE("A64: REV32", "[a64]") { TEST_CASE("A64: REV16", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xdac00400); // REV16 X0, X0 env.code_mem.emplace_back(0x5ac00421); // REV16 W1, W1 @@ -274,9 +254,7 @@ TEST_CASE("A64: REV16", "[a64]") { TEST_CASE("A64: SSHL", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SSHL(V4.B16(), V4.B16(), V0.B16()); @@ -310,9 +288,7 @@ TEST_CASE("A64: SSHL", "[a64]") { TEST_CASE("A64: USHL", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.USHL(V4.B16(), V4.B16(), V0.B16()); @@ -358,9 +334,7 @@ TEST_CASE("A64: USHL", "[a64]") { TEST_CASE("A64: URSHL", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.URSHL(V0.S4(), V1.S4(), V2.S4()); @@ -391,9 +365,7 @@ TEST_CASE("A64: URSHL", "[a64]") { TEST_CASE("A64: XTN", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0e212803); // XTN v3.8b, v0.8h env.code_mem.emplace_back(0x0e612824); // XTN v4.4h, v1.4s @@ -415,9 +387,7 @@ TEST_CASE("A64: XTN", "[a64]") { TEST_CASE("A64: TBL", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0e000100); // TBL v0.8b, { v8.16b }, v0.8b env.code_mem.emplace_back(0x4e010101); // TBL v1.16b, { v8.16b }, v1.16b @@ -463,9 +433,7 @@ TEST_CASE("A64: TBL", "[a64]") { TEST_CASE("A64: TBX", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0e001100); // TBX v0.8b, { v8.16b }, v0.8b env.code_mem.emplace_back(0x4e011101); // TBX v1.16b, { v8.16b }, v1.16b @@ -511,9 +479,7 @@ TEST_CASE("A64: TBX", "[a64]") { TEST_CASE("A64: AND", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x8a020020); // AND X0, X1, X2 env.code_mem.emplace_back(0x14000000); // B . @@ -534,9 +500,7 @@ TEST_CASE("A64: AND", "[a64]") { TEST_CASE("A64: Bitmasks", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x3200c3e0); // ORR W0, WZR, #0x01010101 env.code_mem.emplace_back(0x320c8fe1); // ORR W1, WZR, #0x00F000F0 @@ -556,9 +520,7 @@ TEST_CASE("A64: Bitmasks", "[a64]") { TEST_CASE("A64: ANDS NZCV", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x6a020020); // ANDS W0, W1, W2 env.code_mem.emplace_back(0x14000000); // B . @@ -613,9 +575,7 @@ TEST_CASE("A64: ANDS NZCV", "[a64]") { TEST_CASE("A64: CBZ", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x34000060); // 0x00 : CBZ X0, label env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 @@ -648,9 +608,7 @@ TEST_CASE("A64: CBZ", "[a64]") { TEST_CASE("A64: TBZ", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x36180060); // 0x00 : TBZ X0, 3, label env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 @@ -694,9 +652,7 @@ TEST_CASE("A64: TBZ", "[a64]") { TEST_CASE("A64: FABD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x6eb5d556); // FABD.4S V22, V10, V21 env.code_mem.emplace_back(0x14000000); // B . @@ -713,9 +669,7 @@ TEST_CASE("A64: FABD", "[a64]") { TEST_CASE("A64: FABS", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4ef8f804); // FABS v4.8h, v0.8h env.code_mem.emplace_back(0x4ea0f825); // FABS v5.4s, v1.4s @@ -737,9 +691,7 @@ TEST_CASE("A64: FABS", "[a64]") { TEST_CASE("A64: FMIN (example)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4ea1f400); // FMIN.4S V0, V0, V1 env.code_mem.emplace_back(0x4ee3f442); // FMIN.2D V2, V2, V3 @@ -761,9 +713,7 @@ TEST_CASE("A64: FMIN (example)", "[a64]") { TEST_CASE("A64: FMAX (example)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e21f400); // FMAX.4S V0, V0, V1 env.code_mem.emplace_back(0x4e63f442); // FMAX.2D V2, V2, V3 @@ -785,9 +735,7 @@ TEST_CASE("A64: FMAX (example)", "[a64]") { TEST_CASE("A64: FMINNM (example)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4ea1c400); // FMINNM.4S V0, V0, V1 env.code_mem.emplace_back(0x4ee3c442); // FMINNM.2D V2, V2, V3 @@ -809,9 +757,7 @@ TEST_CASE("A64: FMINNM (example)", "[a64]") { TEST_CASE("A64: FMAXNM (example)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e21c400); // FMAXNM.4S V0, V0, V1 env.code_mem.emplace_back(0x4e63c442); // FMAXNM.2D V2, V2, V3 @@ -833,9 +779,7 @@ TEST_CASE("A64: FMAXNM (example)", "[a64]") { TEST_CASE("A64: FMAXNM (example 2)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e3bc6fd); // FMAXNM.4S V29, V23, V27 env.code_mem.emplace_back(0x14000000); // B . @@ -887,9 +831,7 @@ TEST_CASE("A64: 128-bit exclusive read/write", "[a64]") { TEST_CASE("A64: CNTPCT_EL0", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xd53be021); // MRS X1, CNTPCT_EL0 env.code_mem.emplace_back(0xd503201f); // NOP @@ -910,9 +852,7 @@ TEST_CASE("A64: CNTPCT_EL0", "[a64]") { TEST_CASE("A64: FNMSUB 1", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x1f618a9c); // FNMSUB D28, D20, D1, D2 env.code_mem.emplace_back(0x14000000); // B . @@ -930,9 +870,7 @@ TEST_CASE("A64: FNMSUB 1", "[a64]") { TEST_CASE("A64: FNMSUB 2", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x1f2ab88e); // FNMSUB S14, S4, S10, S14 env.code_mem.emplace_back(0x14000000); // B . @@ -951,9 +889,7 @@ TEST_CASE("A64: FNMSUB 2", "[a64]") { TEST_CASE("A64: FMADD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x1f5e0e4a); // FMADD D10, D18, D30, D3 env.code_mem.emplace_back(0x14000000); // B . @@ -972,9 +908,7 @@ TEST_CASE("A64: FMADD", "[a64]") { TEST_CASE("A64: FMLA.4S(lane)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4f8f11c0); // FMLA.4S V0, V14, V15[0] env.code_mem.emplace_back(0x4faf11c1); // FMLA.4S V1, V14, V15[1] @@ -1002,9 +936,7 @@ TEST_CASE("A64: FMLA.4S(lane)", "[a64]") { TEST_CASE("A64: FMUL.4S(lane)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4f8f91c0); // FMUL.4S V0, V14, V15[0] env.code_mem.emplace_back(0x4faf91c1); // FMUL.4S V1, V14, V15[1] @@ -1027,9 +959,7 @@ TEST_CASE("A64: FMUL.4S(lane)", "[a64]") { TEST_CASE("A64: FMLA.4S (denormal)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e2fcccc); // FMLA.4S V12, V6, V15 env.code_mem.emplace_back(0x14000000); // B . @@ -1048,9 +978,7 @@ TEST_CASE("A64: FMLA.4S (denormal)", "[a64]") { TEST_CASE("A64: FMLA.4S (0x80800000)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e38cc2b); // FMLA.4S V11, V1, V24 env.code_mem.emplace_back(0x14000000); // B . @@ -1072,9 +1000,7 @@ TEST_CASE("A64: FMLA.4S (0x80800000)", "[a64]") { // x64 performs rounding before flushing-to-zero. TEST_CASE("A64: FMADD (0x80800000)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x1f0f7319); // FMADD S25, S24, S15, S28 env.code_mem.emplace_back(0x14000000); // B . @@ -1093,9 +1019,7 @@ TEST_CASE("A64: FMADD (0x80800000)", "[a64]") { TEST_CASE("A64: FNEG failed to zero upper", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x2ea0fb50); // FNEG.2S V16, V26 env.code_mem.emplace_back(0x2e207a1c); // SQNEG.8B V28, V16 @@ -1114,9 +1038,7 @@ TEST_CASE("A64: FNEG failed to zero upper", "[a64]") { TEST_CASE("A64: FRSQRTS", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24 env.code_mem.emplace_back(0x14000000); // B . @@ -1138,9 +1060,7 @@ TEST_CASE("A64: FRSQRTS", "[a64]") { TEST_CASE("A64: SQDMULH.8H (saturate)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4e62b420); // SQDMULH.8H V0, V1, V2 env.code_mem.emplace_back(0x14000000); // B . @@ -1161,9 +1081,7 @@ TEST_CASE("A64: SQDMULH.8H (saturate)", "[a64]") { TEST_CASE("A64: SQDMULH.4S (saturate)", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x4ea2b420); // SQDMULH.4S V0, V1, V2 env.code_mem.emplace_back(0x14000000); // B . @@ -1184,8 +1102,7 @@ TEST_CASE("A64: SQDMULH.4S (saturate)", "[a64]") { TEST_CASE("A64: This is an infinite loop if fast dispatch is enabled", "[a64]") { A64TestEnv env; - A64::UserConfig conf{}; - conf.callbacks = &env; + A64::UserConfig conf{&env}; conf.optimizations &= ~OptimizationFlag::FastDispatch; A64::Jit jit{conf}; @@ -1202,9 +1119,7 @@ TEST_CASE("A64: This is an infinite loop if fast dispatch is enabled", "[a64]") TEST_CASE("A64: EXTR", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x93d8fef7); // EXTR X23, X23, X24, #63 env.code_mem.emplace_back(0x14000000); // B . @@ -1221,9 +1136,7 @@ TEST_CASE("A64: EXTR", "[a64]") { TEST_CASE("A64: Isolated GetNZCVFromOp", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xaa1f03f5); // MOV X21, XZR env.code_mem.emplace_back(0x912a02da); // ADD X26, X22, #0xa80 @@ -1254,9 +1167,7 @@ TEST_CASE("A64: Isolated GetNZCVFromOp", "[a64]") { TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0xbc4f84be); // LDR S30, [X5], #248 env.code_mem.emplace_back(0x9a0c00ea); // ADC X10, X7, X12 @@ -1352,8 +1263,7 @@ TEST_CASE("A64: Cache Maintenance Instructions", "[a64]") { }; CacheMaintenanceTestEnv env; - A64::UserConfig conf{}; - conf.callbacks = &env; + A64::UserConfig conf{&env}; conf.hook_data_cache_operations = true; A64::Jit jit{conf}; @@ -1380,8 +1290,7 @@ TEST_CASE("A64: Memory access (fastmem)", "[a64]") { char* backing_memory = reinterpret_cast(std::align(page_size, memory_size, buffer_ptr, buffer_size_nconst)); A64FastmemTestEnv env{backing_memory}; - Dynarmic::A64::UserConfig config{}; - config.callbacks = &env; + Dynarmic::A64::UserConfig config{&env}; config.fastmem_pointer = reinterpret_cast(backing_memory); config.fastmem_address_space_bits = address_width; config.recompile_on_fastmem_failure = false; @@ -1414,9 +1323,7 @@ TEST_CASE("A64: Memory access (fastmem)", "[a64]") { TEST_CASE("A64: SQRDMULH QC flag when output invalidated", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x0fbcd38b); // SQRDMULH.2S V11, V28, V28[1] env.code_mem.emplace_back(0x7ef0f8eb); // FMINP.2D D11, V7 @@ -1436,9 +1343,7 @@ TEST_CASE("A64: SQRDMULH QC flag when output invalidated", "[a64]") { TEST_CASE("A64: SDIV maximally", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(0x9ac00c22); // SDIV X2, X1, X0 env.code_mem.emplace_back(0x14000000); // B . @@ -1462,9 +1367,7 @@ TEST_CASE("A64: SDIV maximally", "[a64]") { // const HostLocList any_xmm = { HostLoc::XMM1, HostLoc::XMM2, HostLoc::XMM3, HostLoc::XMM4, HostLoc::XMM5, HostLoc::XMM6 }; TEST_CASE("A64: rand1", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem = {0x2ea2e69a, 0x6f7168e7, 0x7eb0f816, 0x6ebd369d, 0x1e65c302, 0x1e63011c, 0x1e67c349, 0x0f861bd6, 0x9e59cbbc, 0x5e61cb8b, 0x6e218b01, 0x4eb2409f, 0x7f7c2452, 0x7e207a8d, 0xd503369f}; env.code_mem.emplace_back(0x14000000); // B . @@ -1577,10 +1480,7 @@ TEST_CASE("A64: rand1", "[a64]") { TEST_CASE("A64: rand2", "[a64][.]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - jit_user_config.fastmem_pointer = 0xffffffff00000000; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{.callbacks = &env, .fastmem_pointer = 0xffffffff00000000}}; env.code_mem = {0xea80f352, 0x6e65e59d, 0x1e20c343, 0x2e3a7192, 0x2e267249, 0xd500405f, 0x6f01f461, 0x6eb684fc, 0x58028edd, 0x0ea5f5b6, 0x0ea069fb, 0x2e769517, 0x5e066063, 0x1e65c3f5, 0x4f00ff52, 0x93401cf6, 0x1e274248, 0x6f67aaf5, 0x5e0c0782, 0x5ef43f3c, 0x2e6595b7, 0x4e20590f, 0xb35aa451, 0x6ee2c5ed, 0x4e32bf46, 0x2ea1ba8f, 0x2f68a85e, 0x9237d90a, 0x5e23dd10, 0x0e762e32, 0x4e31a8cf, 0xce1f3360, 0x781a4ac0, 0x13834066, 0x5fa8101c, 0x6f7c5594, 0x0e71bb68, 0xbc0b3e8f, 0x785dbbda, 0x6f51e794, 0xce50af75, 0x1ad728ec, 0x6ee0da4c, 0xb84efa14, 0x2eb3f613, 0x4e287ade, 0x4eb8c734, 0x2e83f4e8, 0x0e397c80, 0xd08f93f8, 0xce718e48, 0x0f672a0d, 0x2e9edd40, 0x0e14128b, 0x6f5942e6, 0x8b3a0f03, 0x3c5d16b9, 0x7f7e3743, 0x4f4c54e4, 0x0ea0a9e9, 0x9e59dbe6, 0x6e7ddcd3, 0xcec08377, 0x9ba759f8, 0x2ea5046e, 0x0e24c569, 0xb8979780, 0x4e31b98c, 0x4efe4f46, 0x4ea7c762, 0x7e61c9c6, 0x6e30c880, 0x1ada0c25, 0x4e603a2f, 0xda9d7218, 0x0d40c5d9, 0x5e214b05, 0x9ba9efc5, 0x5e61b81e, 0x6e7bc31c, 0x0e61a163, 0x9e5832d2, 0x4e772248, 0x4e3d17c8, 0x92624f60, 0x7a1a02dc, 0x79891f65, 0x6eb45036, 0x0e321ee8, 0x4e2566f0, 0x4ea02b9b, 0x0f9dcb3d, 0x2e21b9f9, 0x0e21a8c3, 0xda1700bd, 0x6ea0fb38, 0x7e607a0b, 0x72845817, 0x7f61068e, 0x0d60e529, 0x4ea0ca5c, 0x1a94b20f, 0x8b87419d, 0x7ea9ed71, 0x2ea1a86e, 0x4d40c4da, 0x5ea0eada, 0x784ba96e, 0x7eb6ee02, 0x3db1c710, 0x0e217836, 0x7ee0bb96, 0x4e786c08, 0x4e976a08, 0x489ffe86, 0x4e79fc9b, 0x0e21cbce, 0x5ef7fc65, 0x4ea1286d, 0xd29c771e, 0x6f5c2839, 0x0ea00a9d, 0x6ee44c06, 0x5ee1d858, 0x5ef2fda6, 0x7eb0c9fe, 0x7f762791, 0x2e212ae6, 0x4e61c9db, 0x13003c57, 0x5ee1b8f8, 0x0f2396d2, 0x6ea0db1e, 0x0e71ba82, 0xab29c807, 0x6ef8f8b3, 0x1f18d4a1, 0x0e261d15, 0x1e290081, 0x1b0c7d12, 0x4e7771c3, 0xf845f1e4, 0x4d40c9e8, 0xce778452, 0x6eb9879d, 0x6e21c93d, 0xcec0829f, 0x52a0969f, 0x1e772b4f, 0x7ee1da88, 0x5f52fe0a, 0x7f3387b1, 0x5e214850, 0x1e65c025, 0x0e2ca294, 0x2e614829, 0x1e640077, 0x9e240048, 0x4ebe9537, 0x9bb7925e, 0x38b669c5, 0x2840d089, 0x6f43e648, 0x2e662d28, 0x4eabaff3, 0x6e734cc7, 0x0e31baee, 0x7ee0d93c, 0x5e282bde, 0x7e21bba4, 0x4e6c75fa, 0x5ac01217, 0x7f4304af, 0x1e7878ed, 0x1ada2196, 0x7ee1aba3, 0x93407f3c, 0x4f6c34eb, 0x6e3447a9, 0x7e7ae545, 0x5e0802bb, 0x6eeae63a, 0x7ee1da62, 0x5e280bb3, 0xf81d4009, 0x1e603b21, 0x5e281a14, 0x6eb0a99b, 0x1e266a25, 0x0d60cafe, 0x0e0b6194, 0x7a4ed2c5, 0x92b762ec, 0x4e6b5749, 0x3c16a6e5, 0x4ea0a92b, 0x0fa58b6a, 0x5f76148c, 0x6e30c95f, 0x1e6540fd, 0x5e28e40f, 0x0d403fd4, 0x7e30da36, 0x7fda9b51, 0x2ea04bde, 0x1e25c3d2, 0x1ee0434c, 0x5e21d8e7, 0x5ee1ba51, 0x5e61aba9, 0x4e2849fb, 0x5ee098ea, 0x4e60f63d, 0x0f280443, 0x5ee0da27, 0x2e78a6ce, 0x78054afc, 0x4e14286b, 0x4e218bd8, 0x2a3d2551, 0x3a04017a, 0x5f4317cd, 0x0e604a37, 0x9a834614, 0x0e2edf4d, 0x7a51a0a0, 0x5f8e9043, 0x6ea06bb2, 0xaa2857dd, 0x7a1903fc, 0x301ba9ba, 0x9ac929cd, 0x4e061ff0, 0x2e38fcfc, 0x0e2f614a, 0x7ee0d8e4, 0x6e73afda, 0x7f4156f7, 0x0e6078bf, 0x4ee1d9ed, 0x93403fbe, 0xce6f8640, 0x4e3855e3, 0x6f76fe23, 0x112466e8, 0x1e358a90, 0x7f45272c, 0x6ea19a9d, 0x8a696350, 0x1e3900f6, 0x5e61c866, 0x0e3fbfd0, 0x5ee09ad0, 0x0e651d27, 0x4dffc35e, 0x2e20c6ce, 0x0fbe118d, 0x1e656a15, 0xd1357365, 0x0e20a847, 0xce4a835c, 0x4e203905, 0x2e60090d, 0x7f4a27bb, 0x1e64c316, 0xce7d86a4, 0x7ebded2d, 0x6e70a97e, 0x4eb9a42b, 0x0e209bef, 0x6f151730, 0x0e7e30f7, 0x4e724509, 0xd503375f, 0xce58b6ae, 0x5e21a9b8, 0xcb2ca538, 0x5ac01131, 0x6ea19a24, 0xeb40c8b3, 0xc8df7d65, 0x78108341, 0x3218ab9b, 0x0f3da7dd, 0x2e003089, 0x4e21cab5, 0x8aa5c924, 0x1a94950c, 0x123e506f, 0x13117e37, 0x1ee6005b, 0x5ac00647, 0x5eec8cd5, 0x7ef0fb3d, 0x9223272a, 0x5ee0cb02, 0x6e66071d, 0x6ea1dbbf, 0x5e61c903, 0x5ac015ea, 0x93db6206, 0x7e62b5e3, 0x6ea0c87b, 0xdac0090e, 0x48df7d90, 0x6e206ba5, 0x9e2503c2, 0x6e25fc89, 0x4d60e2db, 0x1e3e22a0, 0x2eb81c19, 0x7856ea00, 0x5fbfb22d, 0x1e630244, 0x4e202a83, 0x1f50a722, 0x7f7b55d2, 0x0fae89b9, 0x4e781d73, 0xce738c3a, 0x4f15a591, 0x6e21c7e1, 0x586ff77e, 0x8a5d3592, 0x93401c67, 0x5e61cb86, 0xce6bc2c1, 0x6e393f10, 0x9bb70ec3, 0xdac0098c, 0x4da84b95, 0x7f494476, 0x9ace5c11, 0x7e61ca14, 0x4f7a60ef, 0x1ad32b39, 0x0ea3777f, 0x5e61da7f, 0x4f1404e2, 0x4e3244e2, 0x6e1b1ceb, 0x0dee5aac, 0x4e2f9dc4, 0x5ea1b8c3, 0x1e59f863, 0xd500403f, 0x4e3ae7d0, 0x4ef5c6ea, 0x08dffe3b, 0x6e36f4f6, 0x2e764f29, 0x0e726f23, 0x5f42375b, 0x7f71fc40, 0x6e618aad, 0x93403e5b, 0x0e205976, 0x0e7250c4, 0x6eb0abc9, 0x2e2049f0, 0x5f14754d, 0x7f6ce468, 0x6f950bbe, 0x6e31aa47, 0x4eb83396, 0x0dccc952, 0x2ea1ca90, 0xce69c701, 0xb0bed69e, 0x7c5dec39, 0x4e2868a2, 0x0e591b08, 0x5f34e6dd, 0x3a449184, 0x5e3ce6de, 0x4ea149b7, 0x4e7ad29b, 0xba198503, 0x1f683e8f, 0xfa52f2a7, 0x6e30dffc, 0x4e6c3d17, 0x2eae3248, 0xd503349f, 0x1e60002c, 0x0f180680, 0x9e240049, 0x6f75774e, 0xa90d8678, 0x9ad924c4, 0x7eb0f85b, 0x0e205aaf, 0x7ee08899, 0x5f4bffd8, 0x1b0ff5f3, 0x4ee11dcd, 0x2e218948, 0x0dcb2733, 0x4eac107c, 0x4ea04a53, 0x4e287b44, 0x0e60b82a, 0x5ee0ebbc, 0xce454ff1, 0x5e1761e7, 0x5e09202f, 0x0e0c0754, 0x1e72e6b9, 0x7e21da70, 0x0fbdb20c, 0x5efb8c84, 0xd500401f, 0x3a47526e, 0x1e680acf, 0x7f7375fc, 0xf80522da, 0x4ee60c02, 0x4d40c2e7, 0x6f89096b, 0x7ee1bb6e, 0x5e280b4a, 0x1e3120c8, 0x7eb2ef96, 0x4fd012dd, 0x0f3027ef, 0x4e2078a8, 0xd503201f, 0x2e2312d9, 0x6ebf1c6e, 0x5ee1f8df, 0x4e607a46, 0x6e30c877, 0x6c09d2d1, 0x4e61abd8, 0x0e35267e, 0x6ac17728, 0x0e861aa0, 0x6f63fe26, 0x6f157628, 0x6f30a5f9, 0x4d60cc0c, 0x4e21cb59, 0x2e68a3fb, 0x7efae601, 0x6ea0f82c, 0x9b25ec12, 0x1a1a0305, 0x0e043fe1, 0x6e73c0ed, 0x6ea1b8c0, 0x7e20380b, 0x0f0534e8, 0x1f56bc7d, 0xba0c0128, 0x1e672160, 0x6e7b259b, 0x7ee07b5d, 0x9a820443, 0x4e040581, 0x2f1d87e8, 0x1acd2f5b, 0x6e20794f, 0x2e6a3c93, 0xc8dffe13, 0xce5ab1c6, 0x6eea55f6, 0x4ea039b3, 0x0d602fec, 0x2e246e2f, 0x7857be39, 0xb80608fb, 0x1e67c017, 0x9bcf7f63, 0x0f92d857, 0x5e0812f7, 0x1e210172, 0x7e6128e9, 0x7ea94d41, 0x981179e1, 0x1effb018, 0x2e600828, 0x0eb9c6b2, 0x6ee1baae, 0x4ea0db28, 0x2ea1487b, 0x4ea6c7f0, 0x2e2374c7, 0x7e30d8dd, 0xb9991fa7, 0x4e791e3e, 0x889f7c4b, 0x0e6c753c, 0x1e740ad1, 0x1e244324, 0x1ef33010, 0x5ac01102, 0x9bd97fba, 0x6e290143, 0x1e2220d8, 0x4d8d5aee, 0x6f28570b, 0xfa4ab0c1, 0xdac00b14, 0x7ea1a90e, 0x2e3027d8, 0x6f25a733, 0x4e61a96e, 0x4e1a2fcb, 0x0e22fe0a, 0xc8df7cd0, 0x5e280a55, 0x4e012b20, 0x7e70dbf4, 0x520c5a4e, 0x6ea6c57f, 0x0e861af8, 0xd503233f, 0x889ffe3c, 0x5e274ea9, 0x4e21a89a, 0x0e170c02, 0x6efd4c0b, 0xd5033ebf, 0x6e61a92c, 0x2e205b72, 0x789fb828, 0x0e626e94, 0x2ea6724c, 0x9a10028b, 0x2c6c51fc, 0x5a9de6b9, 0x6e6881f3, 0x5ee0ea6b, 0x0faec36e, 0x0e955bca, 0x1acf206d, 0x7f6f571b, 0x4e286930, 0x12b41ceb, 0x1e770b7a, 0x0ea18ac2, 0x5e282aaf, 0xf2b7fa1e, 0x1ac34311, 0x13167d11, 0x4ea63412, 0x6e758038, 0x2f1d85d6, 0x0f275480, 0x0ead6c71, 0x6e204b69, 0x1e6303f4, 0x5e0031ef, 0x13001e40, 0x7a16006f, 0x6e6ae4c0, 0x0f0f242f, 0x6e674f50, 0x4e606b7a, 0x7e6ee684, 0x1e6b5957, 0x7ea1bbab, 0x7ea0b6cb, 0xce4da241, 0x0ea1b953, 0x0eb2af4b, 0x9ac309d0, 0x6e61d8bd, 0x5ea0d890, 0x5f47d1e7, 0xfa5981ca, 0x1e7f7959, 0x6ef24dd8, 0x0e0a41d1, 0x5ee0e898, 0x4e6038e2, 0x13097d65, 0x6f839088, 0x9e290265, 0x0e208824, 0x2e65af79, 0x6f36a561, 0x9ad3204b, 0x0e21482e, 0x1e24431d, 0xd50330bf, 0x0df641aa, 0x6e602a83, 0xce30505f, 0x5e025238, 0xd503201f, 0x4e608880, 0x4de9c38d, 0x5e0f5348, 0x6eb48ca9, 0x50fda31b, 0x2e251eec, 0x7842ba50, 0xd8a1cd86, 0x2ea09862, 0x0ea09983, 0x2ea333b0, 0x0ea6032c, 0x4f94801b, 0x7e3ee57d, 0x38135e4f, 0xd8fdd9dd, 0x5ee0fcde, 0x9e64033d, 0x6e37f547, 0x6e3dd7ef, 0x13003f3d, 0x0e602f9f, 0x4e7ad014, 0x9b3b6857, 0x5ea0cb67, 0x0eb31c9f, 0x4e7c5372, 0x5e61b8c0, 0x0ea19b23, 0x0ee6e1df, 0x6e63a626, 0x2f139405, 0x7eb0f96d, 0x9e588c63, 0x2e714c3a, 0x6e8c941e, 0x0f61b331, 0x6f01f625, 0x4e78d4ea, 0x6f403709, 0x1a0300da, 0xda0102c8, 0x7e61d9fd, 0xb89469bb, 0x0c838780, 0x2e60a590, 0x4dfd29e1, 0x4e150f2e, 0xce2810bc, 0x5f541591, 0x9ee60259, 0x2eb40e56, 0x5e014027, 0x2ef71faf, 0x4e2d452f, 0x5ee0a813, 0x4eb03301, 0x38443acf, 0x6eabd502, 0x0e2ee71e, 0x5a960364, 0xce7ec596, 0x7efbed09, 0x4ef42ea2, 0x0eb30ea5, 0x5ee0d9f8, 0x6f513552, 0xf89eb3fa, 0x7ea2eca6, 0x9b00cc19, 0xf897409e, 0x1e73485f, 0x381afa77, 0x0f169f3b, 0x5ee1aa70, 0x5e1803ee, 0x0dbf5a4c, 0xce78c7a6, 0x9b0b260c, 0x2ef8fa19, 0x6e70aa4b, 0xce45b805, 0x2ea08e86, 0x4ee0bafd, 0x2ea09a1f, 0x4e218900, 0x6e744f13, 0xce518653, 0xf81b7a68, 0xce45ac5e, 0x7e62e416, 0x1a1b02b6, 0x7e21db48, 0x381daaaf, 0x6b2c0987, 0x0e2ec651, 0x4eae8502, 0x9bde7ca0, 0x6f47201f, 0x7e61a8a3, 0x6e60d5db, 0x4e2879de, 0xf81d194e, 0x4f1b8d05, 0x4d0048b2, 0x6e203be9, 0x4e3e7eb1, 0x0e260ef8, 0x2e688518, 0x7e3fec46, 0xdac00843, 0xf85c8917, 0x2e212a0f, 0x0e8196da, 0xd503359f, 0xce4c81f2, 0x6ee19992, 0x6e21ca79, 0x4d40c1d2, 0x4f5816ef, 0x4e34c3ea, 0x4df7c283, 0x7ef7eeb6, 0x18e276ce, 0xab0d21c0, 0xd5032f7f, 0x4ea00dbf, 0x5ac01251, 0xd0121955, 0x7f1495e4, 0x7ef0fa11, 0x5e24dd9c, 0x9add25b5, 0x0eb2bdef, 0x9e1977c7, 0x6f4b26bd, 0x0e200a9c, 0x9b4f7c00, 0x0ea0392e, 0x7e212a2c, 0x0b248b90, 0x1acc27a1, 0x2e701c90, 0x5ee1b870, 0x5e280aba, 0x5ea0780e, 0x1e264246, 0x4e052d04, 0x0e731dc4, 0xce461997, 0x9a9e9413, 0x3d462048, 0x5ea1fac5, 0x2ea0c8c4, 0x9a030280, 0x2ebda4b8, 0x5eef8614, 0x6eadc4e0, 0xbd035a8f, 0x4e606b84, 0x4eb1aba1, 0x4e286928, 0x4e2858cc, 0x9add0ce9, 0x4e070d65, 0x5fd399d5, 0x0f03fde7, 0x6ee90c74, 0x4ef8e31e, 0x381d986a, 0x5ea0ebf4, 0x5ea0d87e, 0x2e76ac9e, 0x6eb36cd4, 0x2e6e1c4c, 0x2e2feebc, 0x1ace4b03, 0x5ee0db12, 0x5ea0e9b1, 0x2e1c32d5, 0x5fa49a09, 0x0e258737, 0x7e21ca8e, 0xce4f9988, 0x5f7f56a6, 0x0e739766, 0x4e28586c, 0x6e619908, 0xd500401f, 0xf88b9252, 0x6e251c8e, 0x9e20015b, 0x7f1486b9, 0x717c339b, 0x1f31ff70, 0x4ea0eb62, 0x9acb0926, 0x489f7d85, 0x4e209b54, 0x2e84cf03, 0x2e65946c, 0x0e7d80cd, 0xc8dffecc, 0xce668bd8, 0x6e2188af, 0xeb4ada34, 0x2b25ec33, 0x0d40e6e7, 0x4eb2c757, 0x4ec82ad0, 0x7e21cb0a, 0x0e21a847, 0x4e0b1ec0, 0x381e6ac0, 0x6e61c8f5, 0x0f10071c, 0x2ee21daa, 0x5e61ab31, 0x6e218892, 0x2e7e7cb5, 0x6f2826aa, 0x7f6b54df, 0x4eaa2620, 0xdac00034, 0x4f6477be, 0x7e6148ea, 0x4eef1f57, 0x78459aeb, 0x2ebc3f10, 0x2e35f4eb, 0x4fbf19ce, 0xd8d0e58e, 0x2e21bbc7, 0x6ee0cab6, 0x9bc57e3f, 0x2f854037, 0x4e92181c, 0x6e6d1f89, 0x0f305545, 0x4ee19a57, 0x0e887bdf, 0x5e1a4185, 0x7ef0c821, 0x2eb6607c, 0x2ea0d9b8, 0x9e0380f4, 0x2ebf1c83, 0x1e62597d, 0x7f6e2548, 0x5ac00205, 0x4e616adb, 0xce638b8c, 0x5e1653cf, 0x2e6069be, 0x0e2ac641, 0x1e33c76f, 0xce44956d, 0x9bb90d31, 0x1e24c20a, 0x7ee038c1, 0x93407e5e, 0x4e280127, 0xc8df7f7d, 0xba42f263, 0x1e6f199c, 0x6e212889, 0x6e92f60e, 0x6ebdc499, 0x8b9acbf8, 0x4d40c581, 0x3a020250, 0x6e6a6716, 0x9248403b, 0x9081ffea, 0x4e603856, 0x9ad1242b, 0x6f270579, 0x1a070349, 0xcec08133, 0xd503305f, 0x5a1a00ca, 0x2e60b8a2, 0x0e5f28fd, 0x0e31a3da, 0x7e61cbc1, 0xd503399f, 0x5f5e54aa, 0x0eb8bdea, 0x4eba8f10, 0x4e2a2e60, 0x2f3da7d6, 0x1e58e297, 0x6e71aa3e, 0x6b86701a, 0xce4fa5e6, 0x4ee7c463, 0x8a79307f, 0x0ebea541, 0x2e218af4, 0x4e774f8a, 0xb9b95dc5, 0x6e61abd5, 0x4dd1e814, 0x4da72098, 0x98307582, 0x3a512101, 0x7ef95497, 0x1ace5535, 0x5a0c0349, 0x4e28581b, 0x6ebf1c02, 0x5ea1da23, 0x1e274314, 0x5e25dd29, 0x6e75f594, 0x6eaf6ed5, 0x4e214abe, 0x4e064172, 0x2e21c8f4, 0xf84c5b08, 0x1e244312, 0x14000000}; env.code_mem.emplace_back(0x14000000); // B . @@ -1696,9 +1596,7 @@ TEST_CASE("A64: rand2", "[a64][.]") { TEST_CASE("A64: SABD", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SABD(V0.B16(), V3.B16(), V4.B16()); @@ -1756,9 +1654,7 @@ TEST_CASE("A64: SABD", "[a64]") { TEST_CASE("A64: UZP{1,2}.2D", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.UZP1(V2.D2(), V0.D2(), V1.D2()); @@ -1777,9 +1673,7 @@ TEST_CASE("A64: UZP{1,2}.2D", "[a64]") { TEST_CASE("A64: UZP{1,2}.S", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.UZP1(V2.S2(), V0.S2(), V1.S2()); @@ -1802,9 +1696,7 @@ TEST_CASE("A64: UZP{1,2}.S", "[a64]") { TEST_CASE("A64: UZP{1,2}.H", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.UZP1(V2.H4(), V0.H4(), V1.H4()); @@ -1827,9 +1719,7 @@ TEST_CASE("A64: UZP{1,2}.H", "[a64]") { TEST_CASE("A64: UZP{1,2}.B", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.UZP1(V2.B8(), V0.B8(), V1.B8()); @@ -1852,9 +1742,7 @@ TEST_CASE("A64: UZP{1,2}.B", "[a64]") { TEST_CASE("A64: {S,U}MIN.S, {S,U}MAX.S", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMIN(V2.S4(), V0.S4(), V1.S4()); @@ -1898,9 +1786,7 @@ TEST_CASE("A64: {S,U}MIN.S, {S,U}MAX.S", "[a64]") { TEST_CASE("A64: {S,U}MIN.H, {S,U}MAX.H", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMIN(V2.H8(), V0.H8(), V1.H8()); @@ -1944,9 +1830,7 @@ TEST_CASE("A64: {S,U}MIN.H, {S,U}MAX.H", "[a64]") { TEST_CASE("A64: {S,U}MIN.B, {S,U}MAX.B", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMIN(V2.B16(), V0.B16(), V1.B16()); @@ -1990,9 +1874,7 @@ TEST_CASE("A64: {S,U}MIN.B, {S,U}MAX.B", "[a64]") { TEST_CASE("A64: {S,U}MINP.S, {S,U}MAXP.S", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMINP(V2.S2(), V0.S2(), V1.S2()); @@ -2060,9 +1942,7 @@ TEST_CASE("A64: {S,U}MINP.S, {S,U}MAXP.S", "[a64]") { TEST_CASE("A64: {S,U}MINP.H, {S,U}MAXP.H", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMINP(V2.H4(), V0.H4(), V1.H4()); @@ -2130,9 +2010,7 @@ TEST_CASE("A64: {S,U}MINP.H, {S,U}MAXP.H", "[a64]") { TEST_CASE("A64: {S,U}MINP.B, {S,U}MAXP.B", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; code.SMINP(V2.B8(), V0.B8(), V1.B8()); @@ -2206,9 +2084,7 @@ TEST_CASE("A64: {S,U}MINP.B, {S,U}MAXP.B", "[a64]") { TEST_CASE("A64: SQABS", "[a64]") { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; oaknut::VectorCodeGenerator code{env.code_mem, nullptr}; // should set QC flag diff --git a/externals/dynarmic/tests/A64/fibonacci.cpp b/externals/dynarmic/tests/A64/fibonacci.cpp index cbb02d1b01..29dcbdcd72 100644 --- a/externals/dynarmic/tests/A64/fibonacci.cpp +++ b/externals/dynarmic/tests/A64/fibonacci.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2023 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include #include "dynarmic/interface/A64/a64.h" diff --git a/externals/dynarmic/tests/A64/fp_min_max.cpp b/externals/dynarmic/tests/A64/fp_min_max.cpp index 3d997d956d..7aa1ef4407 100644 --- a/externals/dynarmic/tests/A64/fp_min_max.cpp +++ b/externals/dynarmic/tests/A64/fp_min_max.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "./testenv.h" @@ -67,9 +64,7 @@ u32 force_default_nan(u32 value) { template void run_test(u32 instruction, Fn fn) { A64TestEnv env; - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &env; - A64::Jit jit{jit_user_config}; + A64::Jit jit{A64::UserConfig{&env}}; env.code_mem.emplace_back(instruction); // FMAX S0, S1, S2 env.code_mem.emplace_back(0x14000000); // B . diff --git a/externals/dynarmic/tests/A64/fuzz_with_unicorn.cpp b/externals/dynarmic/tests/A64/fuzz_with_unicorn.cpp index 8eda62f21e..1a56a982ef 100644 --- a/externals/dynarmic/tests/A64/fuzz_with_unicorn.cpp +++ b/externals/dynarmic/tests/A64/fuzz_with_unicorn.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "../fuzz_util.h" #include "../rand_int.h" @@ -157,8 +154,7 @@ static u32 GenFloatInst(u64 pc, bool is_last_inst) { } static Dynarmic::A64::UserConfig GetUserConfig(A64TestEnv& jit_env) { - Dynarmic::A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &jit_env; + Dynarmic::A64::UserConfig jit_user_config{&jit_env}; jit_user_config.optimizations &= ~OptimizationFlag::FastDispatch; // The below corresponds to the settings for qemu's aarch64_max_initfn jit_user_config.dczid_el0 = 7; diff --git a/externals/dynarmic/tests/A64/misaligned_page_table.cpp b/externals/dynarmic/tests/A64/misaligned_page_table.cpp index 75ac41e06d..f54aa58641 100644 --- a/externals/dynarmic/tests/A64/misaligned_page_table.cpp +++ b/externals/dynarmic/tests/A64/misaligned_page_table.cpp @@ -10,8 +10,7 @@ TEST_CASE("misaligned load/store do not use page_table when detect_misaligned_access_via_page_table is set", "[a64]") { A64TestEnv env; - Dynarmic::A64::UserConfig conf{}; - conf.callbacks = &env; + Dynarmic::A64::UserConfig conf{&env}; conf.page_table = nullptr; conf.detect_misaligned_access_via_page_table = 128; conf.only_detect_misalignment_via_page_table_on_page_boundary = true; diff --git a/externals/dynarmic/tests/A64/test_invalidation.cpp b/externals/dynarmic/tests/A64/test_invalidation.cpp index cba47dd8ca..fa35b02b7f 100644 --- a/externals/dynarmic/tests/A64/test_invalidation.cpp +++ b/externals/dynarmic/tests/A64/test_invalidation.cpp @@ -12,8 +12,8 @@ using namespace Dynarmic; TEST_CASE("ensure fast dispatch entry is cleared even when a block does not have any patching requirements", "[a64]") { A64TestEnv env; - A64::UserConfig conf{}; - conf.callbacks = &env; + + A64::UserConfig conf{&env}; A64::Jit jit{conf}; REQUIRE(conf.HasOptimization(OptimizationFlag::FastDispatch)); @@ -64,8 +64,8 @@ TEST_CASE("ensure fast dispatch entry is cleared even when a block does not have TEST_CASE("ensure fast dispatch entry is cleared even when a block does not have any patching requirements 2", "[a64]") { A64TestEnv env; - A64::UserConfig conf{}; - conf.callbacks = &env; + + A64::UserConfig conf{&env}; A64::Jit jit{conf}; REQUIRE(conf.HasOptimization(OptimizationFlag::FastDispatch)); diff --git a/externals/dynarmic/tests/A64/testenv.h b/externals/dynarmic/tests/A64/testenv.h index 2c5a500f75..73525242c3 100644 --- a/externals/dynarmic/tests/A64/testenv.h +++ b/externals/dynarmic/tests/A64/testenv.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,8 +8,8 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include #include "dynarmic/interface/A64/a64.h" diff --git a/externals/dynarmic/tests/decoder_tests.cpp b/externals/dynarmic/tests/decoder_tests.cpp index e545309960..2028ac98cd 100644 --- a/externals/dynarmic/tests/decoder_tests.cpp +++ b/externals/dynarmic/tests/decoder_tests.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2020 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include "dynarmic/frontend/A32/decoder/asimd.h" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" diff --git a/externals/dynarmic/tests/fp/FPToFixed.cpp b/externals/dynarmic/tests/fp/FPToFixed.cpp index 570ebcbbd7..31a684a687 100644 --- a/externals/dynarmic/tests/fp/FPToFixed.cpp +++ b/externals/dynarmic/tests/fp/FPToFixed.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "../rand_int.h" #include "dynarmic/common/fp/fpcr.h" diff --git a/externals/dynarmic/tests/fp/mantissa_util_tests.cpp b/externals/dynarmic/tests/fp/mantissa_util_tests.cpp index de29d51865..cff942c73f 100644 --- a/externals/dynarmic/tests/fp/mantissa_util_tests.cpp +++ b/externals/dynarmic/tests/fp/mantissa_util_tests.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "../rand_int.h" #include "dynarmic/common/fp/mantissa_util.h" diff --git a/externals/dynarmic/tests/fp/unpacked_tests.cpp b/externals/dynarmic/tests/fp/unpacked_tests.cpp index 919f21bf2f..827b85ac9e 100644 --- a/externals/dynarmic/tests/fp/unpacked_tests.cpp +++ b/externals/dynarmic/tests/fp/unpacked_tests.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "../rand_int.h" #include "dynarmic/common/fp/fpcr.h" diff --git a/externals/dynarmic/tests/fuzz_util.cpp b/externals/dynarmic/tests/fuzz_util.cpp index 351eb1e10f..12dc850b42 100644 --- a/externals/dynarmic/tests/fuzz_util.cpp +++ b/externals/dynarmic/tests/fuzz_util.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -12,7 +9,7 @@ #include #include -#include "dynarmic/common/assert.h" +#include #include "./rand_int.h" #include "dynarmic/common/fp/fpcr.h" diff --git a/externals/dynarmic/tests/fuzz_util.h b/externals/dynarmic/tests/fuzz_util.h index a0b8666969..9530307725 100644 --- a/externals/dynarmic/tests/fuzz_util.h +++ b/externals/dynarmic/tests/fuzz_util.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -11,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include using Vector = std::array; diff --git a/externals/dynarmic/tests/print_info.cpp b/externals/dynarmic/tests/print_info.cpp index ef8b87bbd1..a8580b7b03 100644 --- a/externals/dynarmic/tests/print_info.cpp +++ b/externals/dynarmic/tests/print_info.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -18,7 +15,7 @@ #include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/llvm_disassemble.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" diff --git a/externals/dynarmic/tests/rsqrt_test.cpp b/externals/dynarmic/tests/rsqrt_test.cpp index 6af71ede64..7adbe39e12 100644 --- a/externals/dynarmic/tests/rsqrt_test.cpp +++ b/externals/dynarmic/tests/rsqrt_test.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2021 MerryMage * SPDX-License-Identifier: 0BSD @@ -9,7 +6,7 @@ #include #include #include -#include "dynarmic/common/common_types.h" +#include #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/externals/dynarmic/tests/test_generator.cpp b/externals/dynarmic/tests/test_generator.cpp index c8f05d06f8..cfdd8ea436 100644 --- a/externals/dynarmic/tests/test_generator.cpp +++ b/externals/dynarmic/tests/test_generator.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2022 MerryMage * SPDX-License-Identifier: 0BSD @@ -18,7 +15,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "./A32/testenv.h" #include "./A64/testenv.h" @@ -26,7 +23,6 @@ #include "./rand_int.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" -#include "dynarmic/common/llvm_disassemble.h" #include "dynarmic/frontend/A32/ITState.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" @@ -400,41 +396,39 @@ Dynarmic::A32::UserConfig GetA32UserConfig(TestEnv& testenv, bool noopt) { template void RunTestInstance(Dynarmic::A32::Jit& jit, - TestEnv& jit_env, - const std::array& regs, - const std::array& vecs, - const std::vector& instructions, - const u32 cpsr, - const u32 fpscr, - const size_t ticks_left, - const bool show_disas) { + TestEnv& jit_env, + const std::array& regs, + const std::array& vecs, + const std::vector& instructions, + const u32 cpsr, + const u32 fpscr, + const size_t ticks_left) { const u32 initial_pc = regs[15]; const u32 num_words = initial_pc / sizeof(typename TestEnv::InstructionType); const u32 code_mem_size = num_words + static_cast(instructions.size()); - if (show_disas) { - fmt::print("instructions:\n"); - auto current_pc = initial_pc; - for (auto instruction : instructions) { - if constexpr (sizeof(decltype(instruction)) == 2) { - fmt::print("{:04x} ?\n", instruction); - } else { - fmt::print("{}", Dynarmic::Common::DisassembleAArch64(instruction, current_pc)); - } - current_pc += sizeof(decltype(instruction)); + fmt::print("instructions:"); + for (auto instruction : instructions) { + if constexpr (sizeof(decltype(instruction)) == 2) { + fmt::print(" {:04x}", instruction); + } else { + fmt::print(" {:08x}", instruction); } - - fmt::print("initial_regs:"); - for (u32 i : regs) - fmt::print(" {:08x}", i); - fmt::print("\n"); - fmt::print("initial_vecs:"); - for (u32 i : vecs) - fmt::print(" {:08x}", i); - fmt::print("\n"); - fmt::print("initial_cpsr: {:08x}\n", cpsr); - fmt::print("initial_fpcr: {:08x}\n", fpscr); } + fmt::print("\n"); + + fmt::print("initial_regs:"); + for (u32 i : regs) { + fmt::print(" {:08x}", i); + } + fmt::print("\n"); + fmt::print("initial_vecs:"); + for (u32 i : vecs) { + fmt::print(" {:08x}", i); + } + fmt::print("\n"); + fmt::print("initial_cpsr: {:08x}\n", cpsr); + fmt::print("initial_fpcr: {:08x}\n", fpscr); jit.ClearCache(); @@ -456,37 +450,36 @@ void RunTestInstance(Dynarmic::A32::Jit& jit, jit.Run(); } - if (show_disas) { - fmt::print("final_regs:"); - for (u32 i : jit.Regs()) { - fmt::print(" {:08x}", i); - } - fmt::print("\n"); - fmt::print("final_vecs:"); - for (u32 i : jit.ExtRegs()) { - fmt::print(" {:08x}", i); - } - fmt::print("\n"); - fmt::print("final_cpsr: {:08x}\n", jit.Cpsr()); - fmt::print("final_fpsr: {:08x}\n", mask_fpsr_cum_bits ? jit.Fpscr() & 0xffffff00 : jit.Fpscr()); - fmt::print("mod_mem: "); - for (auto [addr, value] : jit_env.modified_memory) { - fmt::print("{:08x}:{:02x} ", addr, value); - } - fmt::print("\n"); - fmt::print("interrupts:\n"); - for (const auto& i : jit_env.interrupts) { - std::puts(i.c_str()); - } - fmt::print("===\n"); - jit.DumpDisassembly(); + fmt::print("final_regs:"); + for (u32 i : jit.Regs()) { + fmt::print(" {:08x}", i); } + fmt::print("\n"); + fmt::print("final_vecs:"); + for (u32 i : jit.ExtRegs()) { + fmt::print(" {:08x}", i); + } + fmt::print("\n"); + fmt::print("final_cpsr: {:08x}\n", jit.Cpsr()); + fmt::print("final_fpsr: {:08x}\n", mask_fpsr_cum_bits ? jit.Fpscr() & 0xffffff00 : jit.Fpscr()); + + fmt::print("mod_mem: "); + for (auto [addr, value] : jit_env.modified_memory) { + fmt::print("{:08x}:{:02x} ", addr, value); + } + fmt::print("\n"); + + fmt::print("interrupts:\n"); + for (const auto& i : jit_env.interrupts) { + std::puts(i.c_str()); + } + + fmt::print("===\n"); } Dynarmic::A64::UserConfig GetA64UserConfig(A64TestEnv& jit_env, bool noopt) { - Dynarmic::A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &jit_env; - jit_user_config.optimizations = all_safe_optimizations; + Dynarmic::A64::UserConfig jit_user_config{&jit_env}; + jit_user_config.optimizations &= ~OptimizationFlag::FastDispatch; // The below corresponds to the settings for qemu's aarch64_max_initfn jit_user_config.dczid_el0 = 7; jit_user_config.ctr_el0 = 0x80038003; @@ -498,16 +491,15 @@ Dynarmic::A64::UserConfig GetA64UserConfig(A64TestEnv& jit_env, bool noopt) { template void RunTestInstance(Dynarmic::A64::Jit& jit, - A64TestEnv& jit_env, - const std::array& regs, - const std::array, 32>& vecs, - const std::vector& instructions, - const u32 pstate, - const u32 fpcr, - const u64 initial_sp, - const u64 start_address, - const size_t ticks_left, - const bool show_disas) { + A64TestEnv& jit_env, + const std::array& regs, + const std::array, 32>& vecs, + const std::vector& instructions, + const u32 pstate, + const u32 fpcr, + const u64 initial_sp, + const u64 start_address, + const size_t ticks_left) { jit.ClearCache(); for (size_t jit_rerun_count = 0; jit_rerun_count < num_jit_reruns; ++jit_rerun_count) { @@ -530,53 +522,59 @@ void RunTestInstance(Dynarmic::A64::Jit& jit, jit.Run(); } - if (show_disas) { - fmt::print("instructions:\n"); - auto current_pc = start_address; - for (u32 instruction : instructions) { - fmt::print("{}", Dynarmic::Common::DisassembleAArch64(instruction, current_pc)); - current_pc += 4; - } - - fmt::print("initial_regs:"); - for (u64 i : regs) - fmt::print(" {:016x}", i); - fmt::print("\n"); - fmt::print("initial_vecs:"); - for (auto i : vecs) - fmt::print(" {:016x}:{:016x}", i[0], i[1]); - fmt::print("\n"); - fmt::print("initial_sp: {:016x}\n", initial_sp); - fmt::print("initial_pstate: {:08x}\n", pstate); - fmt::print("initial_fpcr: {:08x}\n", fpcr); - fmt::print("final_regs:"); - for (u64 i : jit.GetRegisters()) - fmt::print(" {:016x}", i); - fmt::print("\n"); - fmt::print("final_vecs:"); - for (auto i : jit.GetVectors()) - fmt::print(" {:016x}:{:016x}", i[0], i[1]); - fmt::print("\n"); - fmt::print("final_sp: {:016x}\n", jit.GetSP()); - fmt::print("final_pc: {:016x}\n", jit.GetPC()); - fmt::print("final_pstate: {:08x}\n", jit.GetPstate()); - fmt::print("final_fpcr: {:08x}\n", jit.GetFpcr()); - fmt::print("final_qc : {}\n", FP::FPSR{jit.GetFpsr()}.QC()); - fmt::print("mod_mem:"); - for (auto [addr, value] : jit_env.modified_memory) - fmt::print(" {:08x}:{:02x}", addr, value); - fmt::print("\n"); - fmt::print("interrupts:\n"); - for (const auto& i : jit_env.interrupts) - std::puts(i.c_str()); - fmt::print("===\n"); - jit.DumpDisassembly(); + fmt::print("instructions:"); + for (u32 instruction : instructions) { + fmt::print(" {:08x}", instruction); } + fmt::print("\n"); + + fmt::print("initial_regs:"); + for (u64 i : regs) { + fmt::print(" {:016x}", i); + } + fmt::print("\n"); + fmt::print("initial_vecs:"); + for (auto i : vecs) { + fmt::print(" {:016x}:{:016x}", i[0], i[1]); + } + fmt::print("\n"); + fmt::print("initial_sp: {:016x}\n", initial_sp); + fmt::print("initial_pstate: {:08x}\n", pstate); + fmt::print("initial_fpcr: {:08x}\n", fpcr); + + fmt::print("final_regs:"); + for (u64 i : jit.GetRegisters()) { + fmt::print(" {:016x}", i); + } + fmt::print("\n"); + fmt::print("final_vecs:"); + for (auto i : jit.GetVectors()) { + fmt::print(" {:016x}:{:016x}", i[0], i[1]); + } + fmt::print("\n"); + fmt::print("final_sp: {:016x}\n", jit.GetSP()); + fmt::print("final_pc: {:016x}\n", jit.GetPC()); + fmt::print("final_pstate: {:08x}\n", jit.GetPstate()); + fmt::print("final_fpcr: {:08x}\n", jit.GetFpcr()); + fmt::print("final_qc : {}\n", FP::FPSR{jit.GetFpsr()}.QC()); + + fmt::print("mod_mem:"); + for (auto [addr, value] : jit_env.modified_memory) { + fmt::print(" {:08x}:{:02x}", addr, value); + } + fmt::print("\n"); + + fmt::print("interrupts:\n"); + for (const auto& i : jit_env.interrupts) { + std::puts(i.c_str()); + } + + fmt::print("===\n"); } } // Anonymous namespace -void TestThumb(size_t num_instructions, size_t num_iterations, bool noopt, bool show_disas) { +void TestThumb(size_t num_instructions, size_t num_iterations, bool noopt) { ThumbTestEnv jit_env{}; Dynarmic::A32::Jit jit{GetA32UserConfig(jit_env, noopt)}; @@ -599,11 +597,11 @@ void TestThumb(size_t num_instructions, size_t num_iterations, bool noopt, bool } regs[15] = start_address; - RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, num_instructions, show_disas); + RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, num_instructions); } } -void TestArm(size_t num_instructions, size_t num_iterations, bool noopt, bool show_disas) { +void TestArm(size_t num_instructions, size_t num_iterations, bool noopt) { ArmTestEnv jit_env{}; Dynarmic::A32::Jit jit{GetA32UserConfig(jit_env, noopt)}; @@ -625,11 +623,11 @@ void TestArm(size_t num_instructions, size_t num_iterations, bool noopt, bool sh } regs[15] = start_address; - RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, num_instructions, show_disas); + RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, num_instructions); } } -void TestA64(size_t num_instructions, size_t num_iterations, bool noopt, bool show_disas) { +void TestA64(size_t num_instructions, size_t num_iterations, bool noopt) { A64TestEnv jit_env{}; Dynarmic::A64::Jit jit{GetA64UserConfig(jit_env, noopt)}; @@ -651,7 +649,7 @@ void TestA64(size_t num_instructions, size_t num_iterations, bool noopt, bool sh instructions.emplace_back(GenRandomA64Inst(static_cast(start_address + 4 * instructions.size()), i == num_instructions - 1)); } - RunTestInstance(jit, jit_env, regs, vecs, instructions, pstate, fpcr, initial_sp, start_address, num_instructions, show_disas); + RunTestInstance(jit, jit_env, regs, vecs, instructions, pstate, fpcr, initial_sp, start_address, num_instructions); } } @@ -679,7 +677,6 @@ int main(int argc, char* argv[]) { const auto instruction_count = str2sz(argv[3]); const auto iterator_count = str2sz(argv[4]); const bool noopt = argc == 6 && (strcmp(argv[5], "noopt") == 0); - const bool show_disas = argc == 6 && (strcmp(argv[5], "disas") == 0); if (!seed || !instruction_count || !iterator_count) { fmt::print("invalid numeric arguments\n"); @@ -689,11 +686,11 @@ int main(int argc, char* argv[]) { detail::g_rand_int_generator.seed(static_cast(*seed)); if (strcmp(argv[1], "thumb") == 0) { - TestThumb(*instruction_count, *iterator_count, noopt, show_disas); + TestThumb(*instruction_count, *iterator_count, noopt); } else if (strcmp(argv[1], "arm") == 0) { - TestArm(*instruction_count, *iterator_count, noopt, show_disas); + TestArm(*instruction_count, *iterator_count, noopt); } else if (strcmp(argv[1], "a64") == 0) { - TestA64(*instruction_count, *iterator_count, noopt, show_disas); + TestA64(*instruction_count, *iterator_count, noopt); } else { fmt::print("unrecognized instruction class\n"); return 1; diff --git a/externals/dynarmic/tests/test_reader.cpp b/externals/dynarmic/tests/test_reader.cpp index dd7fccc7d7..44d6e966ea 100644 --- a/externals/dynarmic/tests/test_reader.cpp +++ b/externals/dynarmic/tests/test_reader.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2023 MerryMage * SPDX-License-Identifier: 0BSD @@ -13,7 +10,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include #include "./A32/testenv.h" #include "./A64/testenv.h" @@ -161,8 +158,7 @@ void RunTestInstance(Dynarmic::A32::Jit& jit, } A64::UserConfig GetA64UserConfig(A64TestEnv& jit_env, bool noopt) { - A64::UserConfig jit_user_config{}; - jit_user_config.callbacks = &jit_env; + A64::UserConfig jit_user_config{&jit_env}; jit_user_config.optimizations &= ~OptimizationFlag::FastDispatch; // The below corresponds to the settings for qemu's aarch64_max_initfn jit_user_config.dczid_el0 = 7; diff --git a/externals/dynarmic/tests/unicorn_emu/a32_unicorn.cpp b/externals/dynarmic/tests/unicorn_emu/a32_unicorn.cpp index 415ad311e5..db704c97df 100644 --- a/externals/dynarmic/tests/unicorn_emu/a32_unicorn.cpp +++ b/externals/dynarmic/tests/unicorn_emu/a32_unicorn.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -10,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include #include #include "../A32/testenv.h" diff --git a/externals/dynarmic/tests/unicorn_emu/a32_unicorn.h b/externals/dynarmic/tests/unicorn_emu/a32_unicorn.h index 79831b8111..d4fe3c41a4 100644 --- a/externals/dynarmic/tests/unicorn_emu/a32_unicorn.h +++ b/externals/dynarmic/tests/unicorn_emu/a32_unicorn.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -19,7 +16,7 @@ # include #endif -#include "dynarmic/common/common_types.h" +#include #include "../A32/testenv.h" diff --git a/externals/dynarmic/tests/unicorn_emu/a64_unicorn.cpp b/externals/dynarmic/tests/unicorn_emu/a64_unicorn.cpp index 42b72bdb91..3c202c7c8e 100644 --- a/externals/dynarmic/tests/unicorn_emu/a64_unicorn.cpp +++ b/externals/dynarmic/tests/unicorn_emu/a64_unicorn.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -8,7 +5,7 @@ #include "./a64_unicorn.h" -#include "dynarmic/common/assert.h" +#include #define CHECKED(expr) \ do { \ diff --git a/externals/dynarmic/tests/unicorn_emu/a64_unicorn.h b/externals/dynarmic/tests/unicorn_emu/a64_unicorn.h index 54f09c3b28..57759605f0 100644 --- a/externals/dynarmic/tests/unicorn_emu/a64_unicorn.h +++ b/externals/dynarmic/tests/unicorn_emu/a64_unicorn.h @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * SPDX-License-Identifier: 0BSD @@ -19,7 +16,7 @@ # include #endif -#include "dynarmic/common/common_types.h" +#include #include "../A64/testenv.h" diff --git a/externals/ffmpeg/CMakeLists.txt b/externals/ffmpeg/CMakeLists.txt index 3222efba70..9eb71418a0 100644 --- a/externals/ffmpeg/CMakeLists.txt +++ b/externals/ffmpeg/CMakeLists.txt @@ -19,17 +19,8 @@ if (NOT WIN32 AND NOT ANDROID) message(FATAL_ERROR "Required program `autoconf` not found.") endif() - include(CPM) - set(CPM_USE_LOCAL_PACKAGES OFF) - - CPMAddPackage( - NAME ffmpeg - URL "https://github.com/ffmpeg/ffmpeg/archive/9c1294eadd.zip" - URL_HASH SHA512=2076e4cb843787c44718c70c4452517273dbc963ef98442f343762ade6c7b9f78555ae9b50a7c628844a15d8cb5e866c04e2f1acfb77093cea4fbc9edf3ad21a - ) - - set(FFmpeg_PREFIX ${ffmpeg_SOURCE_DIR}) - set(FFmpeg_BUILD_DIR ${ffmpeg_BINARY_DIR}) + set(FFmpeg_PREFIX ${PROJECT_SOURCE_DIR}/externals/ffmpeg/ffmpeg) + set(FFmpeg_BUILD_DIR ${PROJECT_BINARY_DIR}/externals/ffmpeg-build) set(FFmpeg_MAKEFILE ${FFmpeg_BUILD_DIR}/Makefile) make_directory(${FFmpeg_BUILD_DIR}) diff --git a/externals/nx_tzdb/tzdb_to_nx/externals/tz/CMakeLists.txt b/externals/nx_tzdb/tzdb_to_nx/externals/tz/CMakeLists.txt index 2312b34dd6..948fe69a23 100644 --- a/externals/nx_tzdb/tzdb_to_nx/externals/tz/CMakeLists.txt +++ b/externals/nx_tzdb/tzdb_to_nx/externals/tz/CMakeLists.txt @@ -24,8 +24,8 @@ if (NOT EXISTS "${TZ_DIR}" OR NOT EXISTS "${TZIF_LIST_FILE}") # separate directory before building. execute_process( COMMAND - ${GIT_PROGRAM} clone --depth=1 "file://${TZ_SOURCE_DIR}" "${TZ_TMP_SOURCE_DIR}" - # No need to be fatal, on SunOS this works fine - COMMAND_ERROR_IS_FATAL ANY + ${GIT_PROGRAM} clone --depth 1 "file://${TZ_SOURCE_DIR}" "${TZ_TMP_SOURCE_DIR}" + COMMAND_ERROR_IS_FATAL ANY ) if (APPLE) diff --git a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/main.cpp b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/main.cpp index 12c12ac268..c1825970ac 100644 --- a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/main.cpp +++ b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/main.cpp @@ -1,6 +1,3 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - #include "tzif.h" #include #include @@ -10,7 +7,7 @@ #include #include #include -#include +#include #include constexpr std::size_t ten_megabytes{(1 << 20) * 10}; @@ -95,7 +92,7 @@ int main(int argc, char *argv[]) { } } - std::uint8_t *buf = new std::uint8_t[filesize]; + u_int8_t *buf = new u_int8_t[filesize]; filesize = read(f, buf, filesize); if (filesize == static_cast(-1)) { @@ -127,7 +124,7 @@ int main(int argc, char *argv[]) { delete[] buf; - std::vector output_buffer; + std::vector output_buffer; tzif_data->ReformatNintendo(output_buffer); filename = "(stdout)"; diff --git a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.cpp b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.cpp index 476afcbc8e..4d2b842741 100644 --- a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.cpp +++ b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.cpp @@ -1,17 +1,14 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - #include "tzif.h" #include #include #include -#include +#include namespace Tzif { -static std::size_t SkipToVersion2(const std::uint8_t *data, std::size_t size) { +static std::size_t SkipToVersion2(const u_int8_t *data, std::size_t size) { char magic[5]; - const std::uint8_t *p{data}; + const u_int8_t *p{data}; std::memcpy(magic, data, 4); magic[4] = '\0'; @@ -31,15 +28,15 @@ static std::size_t SkipToVersion2(const std::uint8_t *data, std::size_t size) { } template constexpr static void SwapEndianess(Type *value) { - std::uint8_t *data = reinterpret_cast(value); + u_int8_t *data = reinterpret_cast(value); union { - std::uint8_t data[sizeof(Type)]; + u_int8_t data[sizeof(Type)]; Type value; } temp; - for (std::uint32_t i = 0; i < sizeof(Type); i++) { - std::uint32_t alt_index = sizeof(Type) - i - 1; + for (u_int32_t i = 0; i < sizeof(Type); i++) { + u_int32_t alt_index = sizeof(Type) - i - 1; temp.data[alt_index] = data[i]; } @@ -55,13 +52,13 @@ static void FlipHeader(Header &header) { SwapEndianess(&header.charcnt); } -std::unique_ptr ReadData(const std::uint8_t *data, std::size_t size) { +std::unique_ptr ReadData(const u_int8_t *data, std::size_t size) { const std::size_t v2_offset = SkipToVersion2(data, size); if (v2_offset == static_cast(-1)) { return nullptr; } - const std::uint8_t *p = data + v2_offset; + const u_int8_t *p = data + v2_offset; Header header; std::memcpy(&header, p, sizeof(header)); @@ -70,10 +67,10 @@ std::unique_ptr ReadData(const std::uint8_t *data, std::size_t size) { FlipHeader(header); const std::size_t data_block_length = - header.timecnt * sizeof(int64_t) + header.timecnt * sizeof(std::uint8_t) + + header.timecnt * sizeof(int64_t) + header.timecnt * sizeof(u_int8_t) + header.typecnt * sizeof(TimeTypeRecord) + - header.charcnt * sizeof(int8_t) + header.isstdcnt * sizeof(std::uint8_t) + - header.isutcnt * sizeof(std::uint8_t); + header.charcnt * sizeof(int8_t) + header.isstdcnt * sizeof(u_int8_t) + + header.isutcnt * sizeof(u_int8_t); if (v2_offset + data_block_length + sizeof(Header) > size) { return nullptr; @@ -84,7 +81,7 @@ std::unique_ptr ReadData(const std::uint8_t *data, std::size_t size) { const auto copy = [](std::unique_ptr &array, int length, - const std::uint8_t *const &ptr) -> const std::uint8_t * { + const u_int8_t *const &ptr) -> const u_int8_t * { const std::size_t region_length = length * sizeof(Type); array = std::make_unique(length); std::memcpy(array.get(), ptr, region_length); @@ -113,16 +110,16 @@ std::unique_ptr ReadData(const std::uint8_t *data, std::size_t size) { return impl; } -static void PushToBuffer(std::vector &buffer, const void *data, +static void PushToBuffer(std::vector &buffer, const void *data, std::size_t size) { - const std::uint8_t *p{reinterpret_cast(data)}; + const u_int8_t *p{reinterpret_cast(data)}; for (std::size_t i = 0; i < size; i++) { buffer.push_back(*p); p++; } } -void DataImpl::ReformatNintendo(std::vector &buffer) const { +void DataImpl::ReformatNintendo(std::vector &buffer) const { buffer.clear(); Header header_copy{header}; @@ -134,7 +131,7 @@ void DataImpl::ReformatNintendo(std::vector &buffer) const { PushToBuffer(buffer, transition_times.get(), header.timecnt * sizeof(int64_t)); PushToBuffer(buffer, transition_types.get(), - header.timecnt * sizeof(std::uint8_t)); + header.timecnt * sizeof(u_int8_t)); PushToBuffer(buffer, local_time_type_records.get(), header.typecnt * sizeof(TimeTypeRecord)); PushToBuffer(buffer, time_zone_designations.get(), diff --git a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.h b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.h index a6eb32a896..62ff3afe15 100644 --- a/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.h +++ b/externals/nx_tzdb/tzdb_to_nx/src/tzdb2nx/tzif.h @@ -1,25 +1,22 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - #pragma once #include #include -#include +#include #include namespace Tzif { typedef struct { char magic[4]; - std::uint8_t version; - std::uint8_t reserved[15]; - std::uint32_t isutcnt; - std::uint32_t isstdcnt; - std::uint32_t leapcnt; - std::uint32_t timecnt; - std::uint32_t typecnt; - std::uint32_t charcnt; + u_int8_t version; + u_int8_t reserved[15]; + u_int32_t isutcnt; + u_int32_t isstdcnt; + u_int32_t leapcnt; + u_int32_t timecnt; + u_int32_t typecnt; + u_int32_t charcnt; } Header; static_assert(sizeof(Header) == 0x2c); @@ -37,9 +34,9 @@ public: #pragma pack(push, 1) typedef struct { - std::uint32_t utoff; - std::uint8_t dst; - std::uint8_t idx; + u_int32_t utoff; + u_int8_t dst; + u_int8_t idx; } TimeTypeRecord; #pragma pack(pop) static_assert(sizeof(TimeTypeRecord) == 0x6); @@ -49,7 +46,7 @@ public: explicit Data() = default; virtual ~Data() = default; - virtual void ReformatNintendo(std::vector &buffer) const = 0; + virtual void ReformatNintendo(std::vector &buffer) const = 0; }; class DataImpl : public Data { @@ -57,19 +54,19 @@ public: explicit DataImpl() = default; ~DataImpl() override = default; - void ReformatNintendo(std::vector &buffer) const override; + void ReformatNintendo(std::vector &buffer) const override; Header header; Footer footer; std::unique_ptr transition_times; - std::unique_ptr transition_types; + std::unique_ptr transition_types; std::unique_ptr local_time_type_records; std::unique_ptr time_zone_designations; - std::unique_ptr standard_indicators; - std::unique_ptr ut_indicators; + std::unique_ptr standard_indicators; + std::unique_ptr ut_indicators; }; -std::unique_ptr ReadData(const std::uint8_t *data, std::size_t size); +std::unique_ptr ReadData(const u_int8_t *data, std::size_t size); } // namespace Tzif diff --git a/externals/renderdoc/renderdoc_app.h b/externals/renderdoc/renderdoc_app.h index 3fdc233165..84ff62b5db 100644 --- a/externals/renderdoc/renderdoc_app.h +++ b/externals/renderdoc/renderdoc_app.h @@ -1,13 +1,10 @@ -// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project -// SPDX-License-Identifier: GPL-3.0-or-later - // SPDX-FileCopyrightText: Baldur Karlsson // SPDX-License-Identifier: MIT /****************************************************************************** * The MIT License (MIT) * - * Copyright (c) 2019-2025 Baldur Karlsson + * Copyright (c) 2019-2023 Baldur Karlsson * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,10 +38,12 @@ #if defined(WIN32) || defined(__WIN32__) || defined(_WIN32) || defined(_MSC_VER) #define RENDERDOC_CC __cdecl -#elif defined(__linux__) || defined(__FreeBSD__) || defined(__sun__) +#elif defined(__linux__) #define RENDERDOC_CC #elif defined(__APPLE__) #define RENDERDOC_CC +#elif defined(__FreeBSD__) +#define RENDERDOC_CC #else #error "Unknown platform" #endif @@ -361,14 +360,14 @@ typedef enum RENDERDOC_OverlayBits eRENDERDOC_Overlay_FrameNumber | eRENDERDOC_Overlay_CaptureList), // Enable all bits - eRENDERDOC_Overlay_All = 0x7ffffff, + eRENDERDOC_Overlay_All = ~0U, // Disable all bits eRENDERDOC_Overlay_None = 0, } RENDERDOC_OverlayBits; // returns the overlay bits that have been set -typedef uint32_t(RENDERDOC_CC *pRENDERDOC_GetOverlayBits)(void); +typedef uint32_t(RENDERDOC_CC *pRENDERDOC_GetOverlayBits)(); // sets the overlay bits with an and & or mask typedef void(RENDERDOC_CC *pRENDERDOC_MaskOverlayBits)(uint32_t And, uint32_t Or); @@ -379,7 +378,7 @@ typedef void(RENDERDOC_CC *pRENDERDOC_MaskOverlayBits)(uint32_t And, uint32_t Or // injected hooks and shut down. Behaviour is undefined if this is called // after any API functions have been called, and there is still no guarantee of // success. -typedef void(RENDERDOC_CC *pRENDERDOC_RemoveHooks)(void); +typedef void(RENDERDOC_CC *pRENDERDOC_RemoveHooks)(); // DEPRECATED: compatibility for code compiled against pre-1.4.1 headers. typedef pRENDERDOC_RemoveHooks pRENDERDOC_Shutdown; @@ -389,7 +388,7 @@ typedef pRENDERDOC_RemoveHooks pRENDERDOC_Shutdown; // If you use your own crash handler and don't want RenderDoc's handler to // intercede, you can call this function to unload it and any unhandled // exceptions will pass to the next handler. -typedef void(RENDERDOC_CC *pRENDERDOC_UnloadCrashHandler)(void); +typedef void(RENDERDOC_CC *pRENDERDOC_UnloadCrashHandler)(); // Sets the capture file path template // @@ -411,14 +410,14 @@ typedef void(RENDERDOC_CC *pRENDERDOC_UnloadCrashHandler)(void); typedef void(RENDERDOC_CC *pRENDERDOC_SetCaptureFilePathTemplate)(const char *pathtemplate); // returns the current capture path template, see SetCaptureFileTemplate above, as a UTF-8 string -typedef const char *(RENDERDOC_CC *pRENDERDOC_GetCaptureFilePathTemplate)(void); +typedef const char *(RENDERDOC_CC *pRENDERDOC_GetCaptureFilePathTemplate)(); // DEPRECATED: compatibility for code compiled against pre-1.1.2 headers. typedef pRENDERDOC_SetCaptureFilePathTemplate pRENDERDOC_SetLogFilePathTemplate; typedef pRENDERDOC_GetCaptureFilePathTemplate pRENDERDOC_GetLogFilePathTemplate; // returns the number of captures that have been made -typedef uint32_t(RENDERDOC_CC *pRENDERDOC_GetNumCaptures)(void); +typedef uint32_t(RENDERDOC_CC *pRENDERDOC_GetNumCaptures)(); // This function returns the details of a capture, by index. New captures are added // to the end of the list. @@ -449,7 +448,7 @@ typedef void(RENDERDOC_CC *pRENDERDOC_SetCaptureFileComments)(const char *filePa const char *comments); // returns 1 if the RenderDoc UI is connected to this application, 0 otherwise -typedef uint32_t(RENDERDOC_CC *pRENDERDOC_IsTargetControlConnected)(void); +typedef uint32_t(RENDERDOC_CC *pRENDERDOC_IsTargetControlConnected)(); // DEPRECATED: compatibility for code compiled against pre-1.1.1 headers. // This was renamed to IsTargetControlConnected in API 1.1.1, the old typedef is kept here for @@ -481,7 +480,7 @@ typedef void(RENDERDOC_CC *pRENDERDOC_GetAPIVersion)(int *major, int *minor, int // This will return 1 if the request was successfully passed on, though it's not guaranteed that // the UI will be on top in all cases depending on OS rules. It will return 0 if there is no current // target control connection to make such a request, or if there was another error -typedef uint32_t(RENDERDOC_CC *pRENDERDOC_ShowReplayUI)(void); +typedef uint32_t(RENDERDOC_CC *pRENDERDOC_ShowReplayUI)(); ////////////////////////////////////////////////////////////////////////// // Capturing functions @@ -512,7 +511,7 @@ typedef void(RENDERDOC_CC *pRENDERDOC_SetActiveWindow)(RENDERDOC_DevicePointer d RENDERDOC_WindowHandle wndHandle); // capture the next frame on whichever window and API is currently considered active -typedef void(RENDERDOC_CC *pRENDERDOC_TriggerCapture)(void); +typedef void(RENDERDOC_CC *pRENDERDOC_TriggerCapture)(); // capture the next N frames on whichever window and API is currently considered active typedef void(RENDERDOC_CC *pRENDERDOC_TriggerMultiFrameCapture)(uint32_t numFrames); @@ -541,7 +540,7 @@ typedef void(RENDERDOC_CC *pRENDERDOC_StartFrameCapture)(RENDERDOC_DevicePointer // Returns whether or not a frame capture is currently ongoing anywhere. // // This will return 1 if a capture is ongoing, and 0 if there is no capture running -typedef uint32_t(RENDERDOC_CC *pRENDERDOC_IsFrameCapturing)(void); +typedef uint32_t(RENDERDOC_CC *pRENDERDOC_IsFrameCapturing)(); // Ends capturing immediately. // diff --git a/externals/sirit/CMakeLists.txt b/externals/sirit/CMakeLists.txt index 782ce8f660..d98a8b5ba5 100644 --- a/externals/sirit/CMakeLists.txt +++ b/externals/sirit/CMakeLists.txt @@ -1,6 +1,6 @@ # This file has been adapted from dynarmic -cmake_minimum_required(VERSION 3.12) +cmake_minimum_required(VERSION 3.8) project(sirit CXX) # Determine if we're built as a subproject (using add_subdirectory)