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[nce] more apple fixes

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Signed-off-by: lizzie <lizzie@eden-emu.dev>
This commit is contained in:
lizzie 2025-08-30 20:02:45 +00:00 • committed by crueter
parent fc28efb5f5
commit 04d9bea6dd
5 changed files with 36 additions and 22 deletions
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10
src/core/arm/nce/arm_nce.cpp
View file

@ -86,7 +86,7 @@ void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
// Restore host callee-saved registers. // Restore host callee-saved registers.
std::memcpy(&CTX_X(19), guest_ctx->host_ctx.host_saved_regs.data(), std::memcpy(&CTX_X(19), guest_ctx->host_ctx.host_saved_regs.data(),
sizeof(guest_ctx->host_ctx.host_saved_regs)); sizeof(guest_ctx->host_ctx.host_saved_regs));
std::memcpy(&fpctx->vregs[8], guest_ctx->host_ctx.host_saved_vregs.data(), std::memcpy(&CTX_Q(8), guest_ctx->host_ctx.host_saved_vregs.data(),
sizeof(guest_ctx->host_ctx.host_saved_vregs)); sizeof(guest_ctx->host_ctx.host_saved_vregs));
// Return from the call on exit by setting pc to x30. // Return from the call on exit by setting pc to x30.
CTX_PC = guest_ctx->host_ctx.host_saved_regs[11]; CTX_PC = guest_ctx->host_ctx.host_saved_regs[11];
@ -125,17 +125,13 @@ bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, voi
} }
bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) { bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext; CTX_DECLARE(raw_context);
auto* fpctx = GetFloatingPointState(host_ctx);
auto& memory = guest_ctx->system->ApplicationMemory(); auto& memory = guest_ctx->system->ApplicationMemory();
// Match and execute an instruction. // Match and execute an instruction.
auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx); if (auto next_pc = MatchAndExecuteOneInstruction(memory, raw_context); next_pc) {
if (next_pc) {
host_ctx.pc = *next_pc; host_ctx.pc = *next_pc;
return true; return true;
} }
// We couldn't handle the access. // We couldn't handle the access.
return HandleFailedGuestFault(guest_ctx, raw_info, raw_context); return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
} }

32
src/core/arm/nce/arm_nce.s
View file

@ -9,9 +9,11 @@
/* static HaltReason Core::ArmNce::ReturnToRunCodeByTrampoline(void* tpidr, Core::GuestContext* ctx, u64 trampoline_addr) */ /* static HaltReason Core::ArmNce::ReturnToRunCodeByTrampoline(void* tpidr, Core::GuestContext* ctx, u64 trampoline_addr) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, "ax", %progbits .section .text._ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, "ax", %progbits
.global _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
.type _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, %function .type _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, %function
#endif
.global _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
_ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm: _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
/* Back up host sp to x3. */ /* Back up host sp to x3. */
/* Back up host tpidr_el0 to x4. */ /* Back up host tpidr_el0 to x4. */
@ -50,9 +52,11 @@ _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
/* static HaltReason Core::ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void* tpidr) */ /* static HaltReason Core::ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void* tpidr) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, "ax", %progbits .section .text._ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, "ax", %progbits
.global _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
.type _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, %function .type _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, %function
#endif
.global _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
_ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv: _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
/* This jumps to the signal handler, which will restore the entire context. */ /* This jumps to the signal handler, which will restore the entire context. */
/* On entry, x0 = thread id, which is already in the right place. */ /* On entry, x0 = thread id, which is already in the right place. */
@ -72,9 +76,11 @@ _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
/* static void Core::ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, void* raw_context) */ /* static void Core::ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, void* raw_context) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, "ax", %progbits .section .text._ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, "ax", %progbits
.global _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
.type _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, %function .type _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, %function
#endif
.global _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
_ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_: _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
stp x29, x30, [sp, #-0x10]! stp x29, x30, [sp, #-0x10]!
mov x29, sp mov x29, sp
@ -100,9 +106,11 @@ _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
/* static void Core::ArmNce::BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context) */ /* static void Core::ArmNce::BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, "ax", %progbits .section .text._ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, "ax", %progbits
.global _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
.type _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, %function .type _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, %function
#endif
.global _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
_ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_: _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
/* Check to see if we have the correct TLS magic. */ /* Check to see if we have the correct TLS magic. */
mrs x8, tpidr_el0 mrs x8, tpidr_el0
@ -131,9 +139,11 @@ _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
/* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */ /* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits .section .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits
.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
.type _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function .type _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function
#endif
.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
_ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_: _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
/* Check to see if we have the correct TLS magic. */ /* Check to see if we have the correct TLS magic. */
mrs x8, tpidr_el0 mrs x8, tpidr_el0
@ -177,9 +187,11 @@ _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
ret ret
/* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */ /* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits .section .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits
.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
.type _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function .type _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function
#endif
.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
_ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_: _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
/* Check to see if we have the correct TLS magic. */ /* Check to see if we have the correct TLS magic. */
mrs x8, tpidr_el0 mrs x8, tpidr_el0
@ -224,9 +236,11 @@ _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
/* static void Core::ArmNce::LockThreadParameters(void* tpidr) */ /* static void Core::ArmNce::LockThreadParameters(void* tpidr) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce20LockThreadParametersEPv, "ax", %progbits .section .text._ZN4Core6ArmNce20LockThreadParametersEPv, "ax", %progbits
.global _ZN4Core6ArmNce20LockThreadParametersEPv
.type _ZN4Core6ArmNce20LockThreadParametersEPv, %function .type _ZN4Core6ArmNce20LockThreadParametersEPv, %function
#endif
.global _ZN4Core6ArmNce20LockThreadParametersEPv
_ZN4Core6ArmNce20LockThreadParametersEPv: _ZN4Core6ArmNce20LockThreadParametersEPv:
/* Offset to lock member. */ /* Offset to lock member. */
add x0, x0, #(TpidrEl0Lock) add x0, x0, #(TpidrEl0Lock)
@ -252,9 +266,11 @@ _ZN4Core6ArmNce20LockThreadParametersEPv:
/* static void Core::ArmNce::UnlockThreadParameters(void* tpidr) */ /* static void Core::ArmNce::UnlockThreadParameters(void* tpidr) */
#ifndef __APPLE__
.section .text._ZN4Core6ArmNce22UnlockThreadParametersEPv, "ax", %progbits .section .text._ZN4Core6ArmNce22UnlockThreadParametersEPv, "ax", %progbits
.global _ZN4Core6ArmNce22UnlockThreadParametersEPv
.type _ZN4Core6ArmNce22UnlockThreadParametersEPv, %function .type _ZN4Core6ArmNce22UnlockThreadParametersEPv, %function
#endif
.global _ZN4Core6ArmNce22UnlockThreadParametersEPv
_ZN4Core6ArmNce22UnlockThreadParametersEPv: _ZN4Core6ArmNce22UnlockThreadParametersEPv:
/* Offset to lock member. */ /* Offset to lock member. */
add x0, x0, #(TpidrEl0Lock) add x0, x0, #(TpidrEl0Lock)

10
src/core/arm/nce/arm_nce_asm_definitions.h
View file

@ -23,11 +23,6 @@
#define GuestContextSp 0xF8 #define GuestContextSp 0xF8
#define GuestContextHostContext 0x320 #define GuestContextHostContext 0x320
#define HostContextSpTpidrEl0 0xE0
#define HostContextTpidrEl0 0xE8
#define HostContextRegs 0x0
#define HostContextVregs 0x60
#define TpidrEl0NativeContext 0x10 #define TpidrEl0NativeContext 0x10
#define TpidrEl0Lock 0x18 #define TpidrEl0Lock 0x18
#define TpidrEl0TlsMagic 0x20 #define TpidrEl0TlsMagic 0x20
@ -35,3 +30,8 @@
#define SpinLockLocked 0 #define SpinLockLocked 0
#define SpinLockUnlocked 1 #define SpinLockUnlocked 1
#define HostContextSpTpidrEl0 0xE0
#define HostContextTpidrEl0 0xE8
#define HostContextRegs 0x0
#define HostContextVregs 0x60

4
src/core/arm/nce/interpreter_visitor.cpp
View file

@ -4,6 +4,7 @@
#include "common/bit_cast.h" #include "common/bit_cast.h"
#include "core/arm/nce/interpreter_visitor.h" #include "core/arm/nce/interpreter_visitor.h"
#include "dynarmic/common/context.h"
namespace Core { namespace Core {
@ -790,7 +791,8 @@ bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt); return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
} }
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context) { std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context) {
CTX_DECLARE(raw_context);
std::span<u64, 31> regs(reinterpret_cast<u64*>(&CTX_X(0)), 31); std::span<u64, 31> regs(reinterpret_cast<u64*>(&CTX_X(0)), 31);
std::span<u128, 32> vregs(reinterpret_cast<u128*>(&CTX_Q(0)), 32); std::span<u128, 32> vregs(reinterpret_cast<u128*>(&CTX_Q(0)), 32);
u64& sp = *reinterpret_cast<u64*>(&CTX_SP); u64& sp = *reinterpret_cast<u64*>(&CTX_SP);

2
src/core/arm/nce/interpreter_visitor.h
View file

@ -105,6 +105,6 @@ private:
const u64& m_pc; const u64& m_pc;
}; };
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context); std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context);
} // namespace Core } // namespace Core