[nce] more apple fixes
Signed-off-by: lizzie <lizzie@eden-emu.dev>
This commit is contained in:
parent
fc28efb5f5
commit
04d9bea6dd
5 changed files with 36 additions and 22 deletions
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@ -86,7 +86,7 @@ void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
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// Restore host callee-saved registers.
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std::memcpy(&CTX_X(19), guest_ctx->host_ctx.host_saved_regs.data(),
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sizeof(guest_ctx->host_ctx.host_saved_regs));
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std::memcpy(&fpctx->vregs[8], guest_ctx->host_ctx.host_saved_vregs.data(),
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std::memcpy(&CTX_Q(8), guest_ctx->host_ctx.host_saved_vregs.data(),
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sizeof(guest_ctx->host_ctx.host_saved_vregs));
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// Return from the call on exit by setting pc to x30.
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CTX_PC = guest_ctx->host_ctx.host_saved_regs[11];
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@ -125,17 +125,13 @@ bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, voi
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}
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bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
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auto* fpctx = GetFloatingPointState(host_ctx);
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CTX_DECLARE(raw_context);
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auto& memory = guest_ctx->system->ApplicationMemory();
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// Match and execute an instruction.
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auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx);
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if (next_pc) {
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if (auto next_pc = MatchAndExecuteOneInstruction(memory, raw_context); next_pc) {
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host_ctx.pc = *next_pc;
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return true;
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}
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// We couldn't handle the access.
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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@ -9,9 +9,11 @@
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/* static HaltReason Core::ArmNce::ReturnToRunCodeByTrampoline(void* tpidr, Core::GuestContext* ctx, u64 trampoline_addr) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, "ax", %progbits
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.global _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
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.type _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, %function
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#endif
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.global _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
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_ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
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/* Back up host sp to x3. */
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/* Back up host tpidr_el0 to x4. */
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@ -50,9 +52,11 @@ _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
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/* static HaltReason Core::ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void* tpidr) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, "ax", %progbits
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.global _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
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.type _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, %function
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#endif
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.global _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
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_ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
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/* This jumps to the signal handler, which will restore the entire context. */
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/* On entry, x0 = thread id, which is already in the right place. */
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@ -72,9 +76,11 @@ _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
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/* static void Core::ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, void* raw_context) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, %function
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#endif
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.global _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
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_ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
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stp x29, x30, [sp, #-0x10]!
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mov x29, sp
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@ -100,9 +106,11 @@ _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
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/* static void Core::ArmNce::BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, %function
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#endif
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.global _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
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_ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
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/* Check to see if we have the correct TLS magic. */
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mrs x8, tpidr_el0
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@ -131,9 +139,11 @@ _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
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/* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function
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#endif
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.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
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_ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
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/* Check to see if we have the correct TLS magic. */
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mrs x8, tpidr_el0
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@ -177,9 +187,11 @@ _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
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ret
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/* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function
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#endif
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.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
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_ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
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/* Check to see if we have the correct TLS magic. */
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mrs x8, tpidr_el0
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@ -224,9 +236,11 @@ _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
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/* static void Core::ArmNce::LockThreadParameters(void* tpidr) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce20LockThreadParametersEPv, "ax", %progbits
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.global _ZN4Core6ArmNce20LockThreadParametersEPv
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.type _ZN4Core6ArmNce20LockThreadParametersEPv, %function
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#endif
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.global _ZN4Core6ArmNce20LockThreadParametersEPv
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_ZN4Core6ArmNce20LockThreadParametersEPv:
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/* Offset to lock member. */
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add x0, x0, #(TpidrEl0Lock)
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@ -252,9 +266,11 @@ _ZN4Core6ArmNce20LockThreadParametersEPv:
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/* static void Core::ArmNce::UnlockThreadParameters(void* tpidr) */
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#ifndef __APPLE__
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.section .text._ZN4Core6ArmNce22UnlockThreadParametersEPv, "ax", %progbits
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.global _ZN4Core6ArmNce22UnlockThreadParametersEPv
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.type _ZN4Core6ArmNce22UnlockThreadParametersEPv, %function
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#endif
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.global _ZN4Core6ArmNce22UnlockThreadParametersEPv
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_ZN4Core6ArmNce22UnlockThreadParametersEPv:
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/* Offset to lock member. */
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add x0, x0, #(TpidrEl0Lock)
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@ -23,11 +23,6 @@
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#define GuestContextSp 0xF8
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#define GuestContextHostContext 0x320
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#define HostContextSpTpidrEl0 0xE0
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#define HostContextTpidrEl0 0xE8
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#define HostContextRegs 0x0
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#define HostContextVregs 0x60
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#define TpidrEl0NativeContext 0x10
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#define TpidrEl0Lock 0x18
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#define TpidrEl0TlsMagic 0x20
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@ -35,3 +30,8 @@
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#define SpinLockLocked 0
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#define SpinLockUnlocked 1
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#define HostContextSpTpidrEl0 0xE0
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#define HostContextTpidrEl0 0xE8
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#define HostContextRegs 0x0
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#define HostContextVregs 0x60
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@ -4,6 +4,7 @@
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#include "common/bit_cast.h"
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#include "core/arm/nce/interpreter_visitor.h"
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#include "dynarmic/common/context.h"
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namespace Core {
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@ -790,7 +791,8 @@ bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
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return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
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}
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std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context) {
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std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context) {
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CTX_DECLARE(raw_context);
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std::span<u64, 31> regs(reinterpret_cast<u64*>(&CTX_X(0)), 31);
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std::span<u128, 32> vregs(reinterpret_cast<u128*>(&CTX_Q(0)), 32);
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u64& sp = *reinterpret_cast<u64*>(&CTX_SP);
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@ -105,6 +105,6 @@ private:
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const u64& m_pc;
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};
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std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context);
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std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context);
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} // namespace Core
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