2025-07-25 02:22:38 +02:00
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// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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2025-05-31 02:33:02 -04:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <cstring>
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#include <iomanip>
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#include <iostream>
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#include <catch2/catch_test_macros.hpp>
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2025-07-25 02:22:38 +02:00
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#include "dynarmic/common/assert.h"
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#include "dynarmic/frontend/A32/decoder/asimd.h"
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#include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
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#include "dynarmic/interface/A32/config.h"
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#include "dynarmic/ir/opcodes.h"
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using namespace Dynarmic;
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TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32][.]") {
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const auto table = A32::GetASIMDDecodeTable<A32::TranslatorVisitor>();
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const auto get_ir = [](const A32::ASIMDMatcher<A32::TranslatorVisitor>& matcher, u32 instruction) {
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ASSERT(matcher.Matches(instruction));
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const A32::LocationDescriptor location{0, {}, {}};
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IR::Block block{location};
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A32::TranslatorVisitor visitor{block, location, {}};
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matcher.call(visitor, instruction);
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return block;
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};
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const auto is_decode_error = [&get_ir](const A32::ASIMDMatcher<A32::TranslatorVisitor>& matcher, u32 instruction) {
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const auto block = get_ir(matcher, instruction);
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2025-09-27 20:41:52 +02:00
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return std::find_if(block.cbegin(), block.cend(), [](auto const& e) {
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return e.GetOpcode() == IR::Opcode::A32ExceptionRaised && A32::Exception(e.GetArg(1).GetU64()) == A32::Exception::DecodeError;
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}) != block.cend();
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};
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for (auto iter = table.cbegin(); iter != table.cend(); ++iter) {
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const u32 expect = iter->GetExpected();
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const u32 mask = iter->GetMask();
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u32 x = 0;
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do {
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const u32 instruction = expect | x;
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const bool iserr = is_decode_error(*iter, instruction);
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const auto alternative = std::find_if(table.cbegin(), iter, [instruction](const auto& m) {
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return m.Matches(instruction);
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});
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const bool altiserr = is_decode_error(*alternative, instruction);
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INFO("Instruction: " << std::hex << std::setfill('0') << std::setw(8) << instruction);
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INFO("Expect: " << std::hex << std::setfill('0') << std::setw(8) << expect);
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INFO("Fill: " << std::hex << std::setfill('0') << std::setw(8) << x);
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2025-09-06 21:40:13 +00:00
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INFO("Name: " << *A32::GetNameASIMD<A32::TranslatorVisitor>(instruction));
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INFO("iserr: " << iserr);
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//INFO("alternative: " << alternative->GetName());
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INFO("altiserr: " << altiserr);
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REQUIRE(((!iserr && alternative == iter) || (iserr && alternative != iter && !altiserr)));
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x = ((x | mask) + 1) & ~mask;
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} while (x != 0);
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}
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2025-09-06 21:40:13 +00:00
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}
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